Topology for controlled power switch module
The present topology for controlled power switch module is concerned with a module where the parasitic inductance of the emitter of the top power switch is optimized to allow the injection of a sample of the overvoltage across this parasitic inductance in the gate drive circuit of the top power switch as a feedback to slow down the slope of the falling gate voltage during an overvoltage that is above a predetermined value.
1. A power switch module, comprising:
a top power switch including a gate, a collector and an emitter, the top power switch configured to be controlled by a top gate driver circuit;
a bottom power switch including a gate, a collector and an emitter, the bottom power switch configured to be controlled by a bottom gate driver circuit;
a top collector trace connected to the collector of the top power switch;
a bottom collector trace connected to the collector of the bottom power switch;
a top emitter trace connected to the emitter of the top power switch;
a bottom emitter trace connected to the emitter of the bottom power switch;
a −Vbus tab connected to the bottom emitter trace;
a +Vbus tab connected to the top collector trace;
at least one phase tab connected to either the bottom collector trace and the top emitter trace; and
an interconnection of the top emitter trace to the bottom collector trace defining a parasitic emitter inductance having such a value that a voltage generated thereacross, during dI/dt, is injected in the top gate driver circuit to create a positive voltage at the emitter of the top power switch to slow down a slope of a gate-emitter voltage (Vge) at turn on.
2. The power switch module of claim 1 , wherein the top power switch includes at least two parallelized power switches.
3. The power switch module of claim 1 , wherein the bottom power switch includes at least two parallelized power switches.
4. The power switch module of claim 1 , wherein the at least one phase tab includes a first phase tab connected to the top emitter trace and a second phase tab connected to the bottom collector trace.
5. The power switch module of claim 4 , wherein the top emitter trace and the bottom collector trace are interconnected via an external interconnection of the first and second phase tabs.
6. The power switch module of claim 1 , wherein the top emitter trace and the bottom collector trace are interconnected via wire bonds.
7. The power switch module of claim 2 , wherein the top emitter trace interconnects the emitters of the parallelized top power switches via a plurality of solder balls mounted to the emitters of the parallelized top power switches onto which the top emitter trace is layered.
8. The power switch module of claim 3 , wherein the bottom emitter trace interconnects the emitters of the parallelized bottom power switches via a plurality of solder balls mounted to the emitters of the parallelized bottom power switches onto which the bottom emitter trace is layered.
9. The power switch module of claim 7 , wherein a) the bottom power switch includes at least two parallelized power switches and b) the bottom emitter trace interconnects the emitters of the parallelized bottom power switches via a plurality of solder balls mounted to the emitters of the parallelized bottom power switches onto which the bottom emitter trace is layered.
10. The power switch module of claim 9 , wherein the at least one phase tab includes a first phase tab connected to the top emitter trace and a second phase tab connected to the bottom collector trace.
11. The power switch module of claim 10 , wherein the top emitter trace and the bottom collector trace are interconnected via an external interconnection of the first and second phase tabs.
12. The power switch module of claim 9 , wherein the top emitter trace and the bottom collector trace are interconnected via wire bonds.
13. A DC to AC inverter, comprising:
a power switch module including;
a top power switch including a gate, a collector and an emitter, the top power switch configured to be controlled by a top gate driver circuit;
a bottom power switch including a gate, a collector and an emitter, the bottom power switch configured to be controlled by a bottom gate driver circuit;
a top collector trace connected to the collector of the top power switch;
a bottom collector trace connected to the collector of the bottom power switch;
a top emitter trace connected to the emitter of the top power switch;
a bottom emitter trace connected to the emitter of the bottom power switch;
a −Vbus tab connected to the bottom emitter trace;
a +Vbus tab connected to the top collector trace;
at least one phase tab connected to either the bottom collector trace and the top emitter trace; and
an interconnection of the top emitter trace to the bottom collector trace defining a parasitic emitter inductance having such a value that a voltage generated thereacross, during dI/dt, is injected in the top gate driver circuit to create a positive voltage at the emitter of the top power switch to slow down a slope of a gate-emitter voltage (Vge) at turn on.
14. A three-phase inverter, comprising:
three power switch modules, each of the modules including:
a top power switch including a gate, a collector and an emitter, the top power switch configured to be controlled by a top gate driver circuit;
a bottom power switch including a gate, a collector and an emitter, the bottom power switch configured to be controlled by a bottom gate driver circuit;
a top collector trace connected to the collector of the top power switch;
a bottom collector trace connected to the collector of the bottom power switch;
a top emitter trace connected to the emitter of the top power switch;
a bottom emitter trace connected to the emitter of the bottom power switch;
a −Vbus tab connected to the bottom emitter trace;
a +Vbus tab connected to the top collector trace;
at least one phase tab connected to either the bottom collector trace and the top emitter trace; and
an interconnection of the top emitter trace to the bottom collector trace defining a parasitic emitter inductance having such a value that a voltage generated thereacross, during dI/dt, is injected in the top gate driver circuit to create a positive voltage at the emitter of the top power switch to slow down a slope of a gate-emitter voltage (Vge) at turn on.