Wiring substrate

1. A wiring substrate comprising:

a first wiring layer;

a first insulation layer covering the first wiring layer and including a via hole that exposes a portion of an upper surface of the first wiring layer; and

a second wiring layer including a wiring pattern and a via, wherein the wiring pattern is formed on an upper surface of the first insulation layer, and the via is formed in the via hole to electrically connect the wiring pattern and the first wiring layer, wherein

the via includes

a via seed layer formed on a wall surface of the first insulation layer that defines the via hole, and

a filled portion formed in the via hole in which the via seed layer is formed, wherein the via hole is filled with the filled portion,

the wiring pattern includes

a wiring seed layer formed on the upper surface of the first insulation layer, and

a pattern layer formed on the wiring seed layer, wherein the pattern layer covers both of the wiring seed layer and the filled portion of the via,

the via seed layer is formed from a metal material that acts to adsorb a plating enhancement agent which enhances formation of the filled portion and the pattern layer in an electrolytic plating solution, and

the wiring seed layer is formed from a metal material that does not act to adsorb the plating enhancement agent as compared to the via seed layer.

2. The wiring substrate according to claim 1 , wherein the via seed layer is formed from copper or a copper alloy, and

the wiring seed layer is formed from nickel or a nickel alloy.

3. The wiring substrate according to claim 1 , wherein the via seed layer resides only in the via hole.