IP Library Granted Patent US 9,817,023
Granted Patent B2
US 9,817,023 · App. 14/201,544 · Granted Nov 14, 2017

Continuous selftest for inertial sensors at 0 Hz

Inventors: Todd F. Miller (Scottsdale, AZ); Marco Fuhrmann (Mesa, AZ); Tom D. Ohe (Tempe, AZ)
Assignee: NXP USA, INC.
G01P21/00G01P15/125
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Quick Facts
Patent No.
US 9,817,023
App. No.
14/201,544
Granted
Nov 14, 2017
Kind
B2
Abstract

A sensor with continuous self test is provided. An exemplary inertial sensor may include one or more self test electrodes so that one or more test signals may be applied to the electrodes during normal operation of the sensor. Normal sensor output may be read and stored during normal operation, when self test signals are typically not applied to the sensor. The normal sensor output provides a baseline for comparison to a sensor offset error detection signal produced when a test signal may be applied to one self test electrode, and also to a sense error detection signal when a test signal may be applied to both self test electrodes.

Claims (13)

1. A system comprising:

an inertial sensing element including a movable electrode disposed between first and second fixed electrodes;

a circuit coupled to the first and second fixed electrodes and configured to apply test voltages thereto; and

a processing device coupled to the sensing element and to the circuit, the processing device configured to perform a self test during operation of the system, the self test comprising a sense error detection process during which the circuit applies voltages having equal potentials to the first and second fixed electrodes at the same time to change the spring constant of the inertial sensing element and the processing device monitors an output signal of the inertial sensing element indicative of the change in a gain of the inertial sensing element.

2. The system of claim 1 wherein the circuit is further configured to maintain the first and second fixed electrodes at about the same potential as the movable electrode during operation of the sensor when the self test is not performed.

3. The system of claim 1 wherein the self test occurs in a plurality of time periods interspersed with normal operation of the sensor during which the self test is not performed.

4. The system of claim 1 wherein the self test further comprises an offset error detection process during which the circuit applies disparate voltages to the first and second electrodes and the processing device monitors an output signal of the sensing element indicative of the deflection of the movable electrode.

5. The system of claim 4 wherein the circuit is configured to hold the first voltage applied to the first fixed electrode substantially constant between the offset error detection process and the sense error detection process, while varying the second voltage applied to the second fixed electrode between the offset error detection process and a sense error detection process.

6. The system of claim 1 wherein the processing device is a dedicated processor.

7. The system of claim 1 wherein the processing device is an ASIC in which the circuit is included.

8. The system of claim 7 wherein the processing device includes an interface circuit to format an output of the processing device for presentation to a data interface.

9. The system of claim 1 wherein the first and second fixed electrodes are dedicated self-test plates, wherein the inertial sensing element further comprises a plurality of sense electrodes, and wherein the movable electrode extends between the dedicated self-test plates and at least one spaced-apart pair of the plurality of sense electrodes.

10. The system of claim 1 wherein the processing device further comprises a sense error generation circuit coupled to the inertial sensing element to generate a sense error test voltage.

Assignments (19)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 19, 2026
From: NXP USA, INC.
To: STMICROELECTRONICS INTERNATIONAL N.V.
Reel/Frame 075126/0880 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040626 FRAME: 0683. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME EFFECTIVE NOVEMBER 7, 2016. Recorded Jan 12, 2017
From: NXP SEMICONDUCTORS USA, INC. (MERGED INTO); FREESCALE SEMICONDUCTOR, INC. (UNDER)
To: NXP USA, INC.
Reel/Frame 041414/0883 →
CHANGE OF NAME Recorded Nov 16, 2016
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 040626/0683 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT APPLICATION NUMBERS 12222918, 14185362, 14147598, 14185868 & 14196276 PREVIOUSLY RECORDED AT REEL: 037458 FRAME: 0479. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded May 12, 2016
From: CITIBANK, NA
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 038665/0498 →
CORRECTIVE ASSIGNMENT TO CORRECT THE APPLICATION NUMBERS PREVIOUSLY RECORDED AT REEL: 037458 FRAME: 0438. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded May 12, 2016
From: CITIBANK, NA
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 038665/0136 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 7, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037458/0438 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 7, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037458/0479 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0763 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 26, 2014
From: OHE, TOM D.
To: FREESCALE SEMICONDUCTOR INC.
Reel/Frame 033608/0955 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 11, 2014
From: MILLER, TODD F.
To: FREESCALE SEMICONDUCTOR INC.
Reel/Frame 033075/0472 →
SUPPLEMENT TO SECURITY AGREEMENT Recorded May 7, 2014
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 032845/0522 →
SUPPLEMENT TO SECURITY AGREEMENT Recorded May 7, 2014
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 032845/0497 →
SUPPLEMENT TO SECURITY AGREEMENT Recorded May 7, 2014
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 032845/0442 →
Continuity (2)
Continuation 12271841 · Nov 15, 2008
Related Publication 20140182351A1 · Jul 3, 2014