Selectively deposited spacer film for metal gate sidewall protection

1. A method of fabricating a fin field-effect transistor (FinFET) device, the method comprising:

forming a carbon-based layer on a plurality of gate structures formed on a semiconductor substrate, each gate structure overlying at least one fin formed on the semiconductor substrate, and the carbon-based layer covering sidewalls of the gate structures;

forming a metal silicide layer overlying the carbon-based layer;

removing the metal silicide layer and carbon-based layer; and

depositing a conductive material between adjacent gate structures.

2. The method of claim 1 , wherein the carbon-based layer is formed on underlying oxide and nitride layers.

3. The method of claim 1 , wherein the forming a carbon-based layer comprises exposing the plurality of gate structures to a gas mixture of hydrogen, ammonia, acetylene, and helium.

4. The method of claim 3 , wherein a pressure of the gas mixture exposed to the gate structures ranges from about 0.1 to about 100 Torr.

5. The method of claim 4 , wherein the pressure of the gas mixture ranges from about 1 to about 10 Torr.

6. The method of claim 3 , wherein the hydrogen and the acetylene are supplied to the gate structures at a flow rate of about 30 to about 3000 sccm, the ammonia is supplied to the gate structures at a flow rate of about 75 to about 7500, and the helium is supplied to the gate structures at a flow rate of about 150 to 15,000 sccm.

7. The method of claim 1 , wherein the carbon-based layer is formed at a temperature of about 200° C. to about 600° C.

8. The method of claim 1 , wherein the carbon-based layer is formed to a thickness of about 10 nm to about 50 nm.

9. The method of claim 1 , wherein the gas mixture selectively reacts with oxide and nitride layers.

10. The method of claim 1 , wherein the carbon-based layer is removed using an oxygen plasma.

11. A method of fabricating a fin field-effect transistor (FinFET) device, the method comprising:

forming a plurality of fins on a semiconductor substrate;

forming a plurality of gate structures, each gate structure overlying at least one fin;

forming source and drain regions on the fins adjacent the gate structures;

forming an interlayer dielectric on the plurality of fins and gate structures;

forming openings in the interlayer dielectric exposing the source and drain regions;

forming a carbon-based layer on sidewalls of the openings;

forming a metal silicide layer overlying the carbon-based layer;

removing the metal silicide layer and carbon-based layer; and

depositing a conductive material in the openings.

12. The method of claim 11 , wherein the forming openings in the interlayer dielectric exposes one or more gate structures.

13. The method of claim 11 , wherein the forming a metal silicide layer comprises depositing a silicide at a temperature of about 50° C. to about 150° C.

14. The method of claim 11 , wherein the metal silicide layer is removed using an acidic etchant and the carbon-based layer is removed using an oxygen plasma.

15. The method of claim 11 , wherein the forming a carbon-based layer comprises supplying a gas mixture of hydrogen, ammonia, acetylene, and helium to the openings.

16. The method of claim 15 , wherein the gas mixture is supplied at a pressure in a range of from about 0.1 to about 100 Torr, and at a temperature of about 200° C. to about 600° C.

17. The method of claim 15 , wherein the hydrogen and the acetylene are supplied to the openings at a flow rate of about 30 to about 3000 sccm, the ammonia is supplied to the gate structures at a flow rate of about 75 to about 7500, and the helium is supplied to the gate structures at a flow rate of about 150 to 15,000 sccm.

18. A method of fabricating a fin field-effect transistor (FinFET) device, the method comprising:

forming a plurality of gate structures on a semiconductor substrate, each gate structure overlying at least one fin;

forming source and drain regions on the at least one fin adjacent the gate structures;

forming an interlayer dielectric on the plurality of fins and gate structures;

forming openings in the interlayer dielectric exposing the source and drain regions;

forming a carbon-based layer on sidewalls of the openings by supplying a gas mixture of hydrogen, ammonia, acetylene, and helium to the openings;

removing the carbon-based layer; and

depositing a conductive material in the openings.

19. The method of claim 18 , wherein the hydrogen and the acetylene are supplied to the openings at a flow rate of about 30 to about 3000 sccm, the ammonia is supplied to the gate structures at a flow rate of about 75 to about 7500, and the helium is supplied to the gate structures at a flow rate of about 150 to 15,000 sccm.

20. The method of claim 18 , further comprising forming a metal silicide layer in the openings after forming the carbon based layer, and removing the metal silicide layer before removing the carbon-based layer.