Shift register, display device and method for driving shift register
The present invention provides a shift register, in which first and second shifting modules are turned on by the first input module according to a first clock signal; the first shifting module shiftingly outputs a first input signal when it is on; a first reset module turns off the first shifting module according to a third clock signal and outputs the first input signal; the second shifting module shiftingly outputs a second input signal when it is on; a second input module outputs a turning-on signal or a turning-off signal to a second reset module according to the first clock signal; a second reset module outputs the second input signal when it is turned on; and a third input module turns off the second shifting module according to the second clock signal. The first, second and third clock signals have a same clock period and a same duty cycle.
1. A shift register, including a first input module, a second input module, a third input module, a first shifting module, a second shifting module, a first reset module and a second reset module, wherein
the first input module is connected with a first input terminal of the shift register, the first shifting module and the second shifting module, and is configured to output a first turning-on signal to the first shifting module and the second shifting module according to a first clock signal;
the first shifting module has an output terminal connected to a first output terminal of the shift register, and is configured to be turned on when receiving the first turning-on signal and shiftingly output a first input signal inputted by the first input terminal;
the first reset module is connected with the first input terminal and the first shifting module and has an output terminal connected to the first output terminal of the shift register, and is configured to turn off the first shifting module according to a third clock signal and output the first input signal when the first shifting module is turned off so as to perform reset;
the second shifting module has an output terminal connected to a second output terminal of the shift register, and is configured to be turned on when receiving the first turning-on signal and shiftingly output a second input signal inputted by a second input terminal of the shift register;
the second input module is connected with the second input terminal and the second reset module, and is configured to output a second turning-on signal or a turning-off signal to the second reset module according to the first clock signal;
the second reset module has an output terminal connected to the second output terminal, and is configured to be turned on when receiving the second turning-on signal and output the second input signal so as to perform reset;
the third input module is connected with the second input terminal and the second shifting module, and is configured to turn off the second shifting module according to a second clock signal; and wherein
the first clock signal, the second clock signal and the third clock signal are a set of clock signals having a same clock period and a same duty cycle.
2. The shift register according to claim 1 , wherein the first input module includes a first transistor, which has a control electrode connected to a first clock signal terminal, a first electrode connected to the first input terminal and serving as an input terminal of the first input module, and a second electrode connected to an input terminal of the first shifting module and serving as an output terminal of the first input module, the first clock signal terminal being configured to allow the first clock signal to be inputted therethrough.
3. The shift register according to claim 1 , wherein the first shifting module includes a sixth transistor and a second storage capacitor,
a control electrode of the sixth transistor being connected to an output terminal of the first input module and serving as an input terminal of the first shifting module, a first electrode of the sixth transistor serving as the output terminal of the first shifting module, and a second electrode of the sixth transistor being connected to a second clock signal terminal;
the second clock signal terminal being configured to allow the second clock signal to be inputted therethrough; and
a first end of the second storage capacitor being connected to the first electrode of the sixth transistor, and a second end of the second storage capacitor being connected to the control electrode of the sixth transistor.
4. The shift register according to claim 1 , wherein the first reset module includes a second transistor, a third transistor, a fourth transistor, a fifth transistor and a first storage capacitor,
a control electrode of the third transistor being connected to the first input terminal, a first electrode of the third transistor being connected to a first-level input terminal, and a second electrode of the third transistor being connected to a control electrode of the fifth transistor;
the first-level input terminal being configured to allow a first-level signal to be inputted therethrough;
a first electrode of the fifth transistor being connected to the first electrode of the third transistor, and a second electrode of the fifth transistor serving as an output terminal of the first reset module;
a control electrode of the second transistor being connected to the second electrode of the third transistor, a first electrode of the second transistor being connected to the first-level input terminal, and a second electrode of the second transistor being connected to an input terminal of the first shifting module;
a first end of the first storage capacitor being connected to the first electrode of the fifth transistor, and a second end of the first storage capacitor being connected to the control electrode of the fifth transistor;
a control electrode of the fourth transistor being connected to a third clock signal terminal, a first electrode of the fourth transistor being connected to the second electrode of the third transistor, and a second electrode of the fourth transistor being connected to a second-level input terminal;
the third clock signal terminal being configured to allow the third clock signal to be inputted therethrough; and
the second-level input terminal being configured to allow a second-level signal to be inputted therethrough, the first level being one of a high level and a low level, and the second level being the other.
5. The shift register according to claim 1 , wherein the second input module includes a seventh transistor,
a control electrode of the seventh transistor being connected to the first clock signal terminal, a first electrode of the seventh transistor being connected to the second input terminal and serving as an input terminal of the second input module, and a second electrode of the seventh transistor being connected to an input terminal of the second reset module and serving as an output terminal of the second input module; and
the first clock signal terminal being configured to allow the first clock signal to be inputted therethrough.
6. The shift register according to claim 5 , wherein the second input module further includes a thirteenth transistor,
a control electrode of the thirteenth transistor being connected to the first output terminal, a first electrode of the thirteenth transistor being connected to the first electrode of the seventh transistor, and a second electrode of the thirteenth transistor being connected to the second electrode of the seventh transistor.
7. The shift register according to claim 1 , wherein the second reset module includes a fourth storage capacitor and a twelfth transistor,
a control electrode of the twelfth transistor being connected to an output terminal of the second input module and serving as an input terminal of the second reset module, a first electrode of the twelfth transistor serving as an output terminal of the second reset module, and a second electrode of the twelfth transistor being connected to a second-level input terminal;
the second-level input terminal being configured to allow a second-level signal to be inputted therethrough;
a first end of the fourth storage capacitor being connected to the control electrode of the twelfth transistor, and a second end of the fourth storage capacitor being connected to the second-level input terminal.
8. The shift register according to claim 1 , wherein the second reset module includes a fourth storage capacitor and a twelfth transistor,
a control electrode of the twelfth transistor being connected to an output terminal of the second input module and serving as an input terminal of the second reset module, a first electrode of the twelfth transistor serving as an output terminal of the second reset module, and a second electrode of the twelfth transistor being connected to a second-level input terminal;
the second-level input terminal being configured to allow a second-level signal to be inputted therethrough;
a first end of the fourth storage capacitor being connected to the control electrode of the twelfth transistor, and a second end of the fourth storage capacitor being connected to a second clock signal terminal; and
the second clock signal terminal being configured to allow the second clock signal to be inputted therethrough.
9. The shift register according to claim 1 , wherein the second shifting module includes an eighth transistor, an eleventh transistor and a third storage capacitor,
a control electrode of the eighth transistor being connected to an input terminal of the first shifting module, a first electrode of the eighth transistor being connected to a control electrode of the eleventh transistor, and a second electrode of the eighth transistor being connected to a second-level input terminal;
the second-level input terminal being configured to allow a second-level signal to be inputted therethrough;
a control electrode of the eleventh transistor being connected to an output terminal of the third input module, a first electrode of the eleventh transistor being connected to a first clock signal terminal, and a second electrode of the eleventh transistor serving as the output terminal of the second shifting module;
the first clock signal terminal being configured to allow the first clock signal to be inputted therethrough;
a first end of the third storage capacitor being connected a the first-level input terminal, and a second end of the third storage capacitor being connected to the control electrode of the eleventh transistor;
the first-level input terminal being configured to allow a first-level signal to be inputted therethrough, the first level being one of a high level and a low level, and the second level being the other.
10. The shift register according to claim 1 , wherein the third input module comprises a ninth transistor and a tenth transistor,
a control electrode of the tenth transistor being connected to a second clock signal terminal, a first electrode of the tenth transistor connected to the first-level input terminal, and a second electrode of the tenth transistor being connected to a first electrode of the ninth transistor;
the second clock signal terminal being configured to allow the second clock signal to be inputted therethrough;
the first-level input terminal being configured to input a first-level signal;
a control electrode of the ninth transistor being connected to the second input terminal, and a second electrode of the ninth transistor being connected to the second shifting module and serving as an output terminal of the third input module.
11. The shift register according to claim 1 , wherein the first input module, the second input module, the third input module, the first shifting module, the second shifting module, the first reset module and the second reset module include transistors, and wherein
all of the transistors are P-type transistors.
12. The shift register according to claim 1 , wherein the first input module, the second input module, the third input module, the first shifting module, the second shifting module, the first reset module and the second reset module include transistors, and wherein
all of the transistors are N-type transistors.
13. The shift register according to claim 1 , wherein the first input module, the second input module, the third input module, the first shifting module, the second shifting module, the first reset module and the second reset module include transistors, and wherein
a part of the transistors are P-type transistors, and remaining part of the transistors are N-type transistors.
14. The shift register according to claim 1 , wherein the first input signal is one of a high-level signal superimposed with a low-level pulse and a low-level signal superimposed with a high-level pulse, and the second input signal is the other;
a sum of pulse widths of the first input signal and the second input signal equals to the clock period;
the pulses of the first input signal and the second input signal start at a same time;
effective signal widths of the first clock signal, the second clock signal and the third clock signal are equal to the pulse width of the first input signal, a delay time for the second clock signal relative to the first clock signal is equal to the pulse width of the first input signal, and a delay time for the third clock signal relative to the second clock signal is equal to the pulse width of the first input signal.
15. The shift register according to claim 14 , wherein the pulse width of the first input signal is equal to one third of the clock period, and the pulse width of the second input signal is equal to two thirds of the clock period.
16. A display device, including the shift register according to claim 1 .
17. A method for driving the shift register according to claim 1 , including the following steps:
a shift outputting step, in which the first input module and the second input module are turned on, the first shifting module and the second shifting module are turned on by the first input module, the second reset module is turned off by the second input module, the first shifting module shiftingly outputs the first input signal inputted through the first input terminal, and the second shifting module shiftingly outputs the second input signal inputted through the second input terminal; and
a reset output step, in which the first reset module, the second input module and the third input module are turned on, the first shifting module is turned off by the first reset module, the second reset module is turned on by the second input module, the second shifting module is turned off by the third input module, the first reset module outputs the first input signal, and the second reset module outputs the second input signal.
18. The method according to claim 17 , wherein the first input signal is one of a high-level signal superimposed with a low-level pulse and a low-level signal superimposed with a high-level pulse, and the second input signal is the other; a sum of pulse widths of the first input signal and the second input signal equals to the clock period; the pulses of the first input signal and the second input signal start at a same time; effective signal widths of the first clock signal, the second clock signal and the third clock signal are equal to the pulse width of the first input signal, a delay time for the second clock signal relative to the first clock signal is equal to the pulse width of the first input signal, and a delay time for the third clock signal relative to the second clock signal is equal to the pulse width of the first input signal; and wherein
the method for driving the shift register includes the following steps:
in a first stage, the first clock signal is active, the first input module and the second input module are turned on, the first shifting module and the second shifting module are turned on by the first input module, the second reset module is turned off by the second input module, the first shifting module outputs an inverted signal of the first input signal, and the second shifting module outputs an inverted signal of the second input signal;
in a second stage, the second clock signal is active, the first input module and the second input module are turned off, the first shifting module and the second shifting module are maintained in the on state, the second reset module is maintained in the off state, the first shifting module outputs the inverted signal of the first input signal, and the second shifting module outputs the second input signal;
in a third stage, the third clock signal is active, the first input module, the second input module and the second reset module are maintained in the off state, the second reset module is maintained in the on state, the first reset module is turned on, the first shifting module is turned off by the first reset module, the first reset module outputs the first input signal, and the second shifting module outputs an inverted signal of the second input signal;
in a fourth stage, the first clock signal is active, the first input module and the second input module are turned on, the first shifting module is turned off by the first input module, the second reset module is turned on by the second input module, the first reset module and the second shifting module are maintained in the on state, the first reset module outputs the first input signal, and the second shifting module and/or the second reset module output the second input signal; and
in a fifth stage, the second clock signal is active, the first input module and second input module are turned off, the third input module is turned on, the second shifting module is turned off by the third input module, the first shifting module is maintained in the off state, the first reset module and the second reset module are maintained in the on state, the first reset module outputs the first input signal, and the second reset module outputs the second input signal.
19. The method according to claim 18 , wherein the pulse width of the first input signal is equal to one third of the clock period, and the pulse width of the second input signal is equal to two thirds of the clock period.
20. The method according to claim 18 , wherein the first, second and third clock signals have an effective signal level equal to the pulse level of the first input signal, which is either a low level or a high level;
in the first stage, the first shifting module outputs the second clock signal, and the second shifting module outputs the first clock signal;
in the second stage, the first shifting module outputs the second clock signal, and the second shifting module outputs the first clock signal;
in the third stage, the first reset module outputs the first input signal, and the second shifting module outputs the first clock signal;
in the fourth stage, the first reset module outputs the first input signal, the second shifting module outputs the first clock signal, and/or the second reset module outputs the second input signal; and
in the fifth stage, the first reset module outputs the first input signal, and the second reset module outputs the second input signal.