IP Library Granted Patent US 9,831,125
Granted Patent B2
US 9,831,125 · App. 15/131,704 · Granted Nov 28, 2017

Method for manufacturing semiconductor device

Inventors: Satoshi Wakatsuki (Mie, JP); Hiroshi Nakazawa (Oita, JP); Atsuko Sakata (Mie, JP)
Assignee: Toshiba Memory Corporation
H01L21/76897H01L21/7682H01L21/76883H01L21/76886
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Quick Facts
Patent No.
US 9,831,125
App. No.
15/131,704
Granted
Nov 28, 2017
Kind
B2
Abstract

According to one embodiment, a method for manufacturing a semiconductor device includes forming a silicon film on an upper surface side, a lower surface side, and a side surface side of an air gap, while leaving part of the air gap between the silicon film formed on the upper surface side and the silicon film formed on the lower surface side. The method includes forming a metal film on a side surface of the slit. The method includes forming a plurality of metal silicide layers between the second layers by causing reaction between the metal film and the silicon film. The method includes removing unreacted part of the metal film formed on the side surface of the slit.

Claims (35)

1. A method for manufacturing a semiconductor device, comprising:

forming a stacked body above a substrate, the stacked body including a plurality of first layers and a plurality of second layers, the first and second layers including a first layer and a second layer alternately stacked;

forming a slit extending in a stacking direction in the stacked body;

removing the first layers which are alternately stacked and exposed to the slit by etching through the slit to form an air gap between the second layers, the air gap communicating with the slit;

forming a silicon film on an upper surface side of the air gap, a lower surface side of the air gap, and a side surface side of the air gap, the side surface side being different from the slit side, while leaving part of the air gap between the silicon film formed on the upper surface side of the air gap and the silicon film formed on the lower surface side of the air gap;

after the forming the silicon film, forming a metal film on a side surface of the slit;

forming a plurality of metal silicide layers between the second layers by causing reaction between the metal film and the silicon film; and

removing unreacted part of the metal film formed on the side surface of the slit.

2. The method according to claim 1 , wherein the metal film is formed also in the part of the air gap.

3. The method according to claim 1 , wherein the silicon film is not interposed between a side surface on the slit side of the second layer and the metal film.

4. The method according to claim 3 , wherein

the silicon film is formed conformally along the side surface of the second layer, the upper surface side of the air gap, the lower surface side of the air gap, and the side surface side of the air gap, and

before the forming the metal film, the silicon film formed on the side surface of the second layer is removed.

5. The method according to claim 4 , wherein the silicon film formed on the side surface of the second layer is removed after occluding an opening on the slit side of the part of the air gap with a cover silicon film.

6. The method according to claim 4 , wherein the silicon film covering a corner of the side surface of the second layer and the upper surface side of the air gap, and the silicon film covering a corner of the side surface of the second layer and the lower surface side of the air gap occlude an opening on the slit side of the part of the air gap.

7. The method according to claim 3 , wherein

the silicon film is formed conformally along the side surface of the second layer, the upper surface side of the air gap, the lower surface side of the air gap, and the side surface side of the air gap, and

before the forming the metal film, the silicon film exposed in the slit and formed along the side surface of the slit is oxidized.

8. The method according to claim 7 , wherein the metal film covers the side surface of the second layer via an oxidized portion of the silicon film.

9. The method according to claim 7 , wherein the silicon film is oxidized by introducing oxygen ions into the slit.

10. The method according to claim 7 , wherein a portion on the slit side of the metal silicide layer is thinner than another portion of the metal silicide layer.

11. The method according to claim 1 , wherein the metal film is a nickel film, and the metal silicide layer is a nickel silicide layer.

12. The method according to claim 11 , wherein the nickel silicide layer primarily contains NiSi.

13. The method according to claim 12 , wherein a height of the part of the air gap is 17% or more of a height of the air gap.

14. The method according to claim 11 , wherein the nickel silicide layer primarily contains Ni 2 Si.

15. The method according to claim 14 , wherein a height of the part of the air gap is 38% or more of a height of the air gap.

16. The method according to claim 1 , further comprising:

forming a columnar part in the stacked body, the columnar part including a semiconductor body extending in the stacking direction and a charge storage part provided between the semiconductor body and the first layer.

17. The method according to claim 1 , wherein the first layer is a silicon nitride layer, and the silicon nitride layer is removed with an etchant containing phosphoric acid.

18. The method according to claim 1 , further comprising:

after the removing the unreacted part of the metal film, removing the second layers by etching through the slit to form an air gap between the metal silicide layers.

19. The method according to claim 18 , wherein the second layer is a silicon oxide layer, and the silicon oxide layer is removed with an etchant containing hydrofluoric acid.

20. The method according to claim 16 , further comprising:

after the removing the unreacted part of the metal film, forming an insulating film on the side surface of the slit; and

forming an interconnect part via the insulating film in the slit.

Assignments (6)
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: K.K. PANGEA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 055669/0401 →
MERGER Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: K.K. PANGEA
Reel/Frame 055659/0471 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 055669/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE POSTAL CODE PREVIOUSLY RECORDED ON REEL 042910 FRAME 0321. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Sep 1, 2017
From: KABUSHIKI KAISHA TOSHIBA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 043747/0290 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 5, 2017
From: KABUSHIKI KAISHA TOSHIBA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 042910/0321 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 20, 2016
From: WAKATSUKI, SATOSHI; NAKAZAWA, HIROSHI; SAKATA, ATSUKO
To: KABUSHIKI KAISHA TOSHIBA
Reel/Frame 038478/0050 →
Continuity (2)
Provisional Application 62266936 · Dec 14, 2015
Related Publication 20170170069A1 · Jun 15, 2017