Laminated ceramic capacitor and method for manufacturing laminated ceramic capacitor
A laminated ceramic capacitor having internal electrodes configured such that Sn is dissolved in Ni, and, in a region of each of the internal electrodes at a depth of 2 nm from a surface thereof facing a ceramic dielectric layer, a CV value representing variation of a Sn/(Ni+Sn) ratio (ratio of number of atoms) is less than or equal to 32%. As a conductive paste for forming the internal electrodes, a conductive paste containing a Ni powder and a tin oxide powder which is represented by SnO or SnO 2 and has a specific surface area of more than or equal to 10 m 2 /g as determined by a BET method is used, or a conductive paste containing a Ni—Sn alloy powder is used, or a conductive paste containing a Ni—Sn alloy powder and a tin oxide powder which is represented by SnO or SnO 2 and has a specific surface area of more than or equal to 10 m 2 /g is used.
1. A laminated ceramic capacitor, comprising:
a ceramic laminated body having a plurality of ceramic dielectric layers and a plurality of internal electrodes arranged to face each other with a ceramic dielectric layer of the plurality of ceramic dielectric layers being interposed therebetween; and
at least two external electrodes arranged on an external surface of the ceramic laminated body, a first of the at least two external electrodes being in conduction with a first set of the plurality of internal electrodes, and a second of the at least two external electrodes being in conduction with a second set of the plurality of internal electrodes, wherein
Sn is dissolved in Ni in the internal electrodes, and
a coefficient of variation value CV of a Sn/(Ni+Sn) ratio, which is represented by [{standard deviation of the Sn/(Ni+Sn) ratio}/{average value of the Sn/(Ni+Sn) ratio}]×100, is less than or equal to 32%, where the Sn/(Ni+Sn) ratio is a ratio of a content of a number of atoms of Sn to a total content of Sn and Ni in a region of each of the plurality of internal electrodes at a depth of 2 nm from a surface thereof facing the ceramic dielectric layer interposed therebetween.
2. The laminated ceramic capacitor according to claim 1 , wherein the plurality of ceramic dielectric layers have a barium titanate-based perovskite compound as a main component thereof.
3. A method for manufacturing a laminated ceramic capacitor, the method comprising:
forming an unfired ceramic laminated body having a plurality of unfired ceramic dielectric layers and a plurality of unfired internal electrode patterns arranged along a plurality of interfaces between the unfired ceramic dielectric layers, the plurality of unfired internal electrode patterns being formed by applying a conductive paste containing a Ni powder and a tin oxide powder which is represented by SnO or SnO 2 and has a specific surface area of more than or equal to 10 m 2 /g as determined by a BET method; and
firing the unfired ceramic laminated body to obtain a ceramic laminated body having a plurality of ceramic dielectric layers and a plurality of internal electrodes arranged along a plurality of interfaces between the ceramic dielectric layers.
4. The method for manufacturing the laminated ceramic capacitor according to claim 3 , wherein the plurality of unfired ceramic dielectric layers have a barium titanate-based perovskite compound as a main component thereof.
5. The method for manufacturing the laminated ceramic capacitor according to claim 3 , further comprising forming at least two external electrodes on an external surface of the ceramic laminated body, a first of the at least two external electrodes being in conduction with a first set of the plurality of internal electrodes, and a second of the at least two external electrodes being in conduction with a second set of the plurality of internal electrodes.
6. The method for manufacturing the laminated ceramic capacitor according to claim 3 , wherein, after firing, the Sn is dissolved in Ni in the internal electrodes, and a coefficient of variation value CV of a Sn/(Ni+Sn) ratio, which is represented by [{standard deviation of the Sn/(Ni+Sn) ratio}/{average value of the Sn/(Ni+Sn) ratio}]×100, is less than or equal to 32%, where the Sn/(Ni+Sn) ratio is a ratio of a content of a number of atoms of Sn to a total content of Sn and Ni in a region of each of the plurality of internal electrodes at a depth of 2 nm from a surface thereof facing the ceramic dielectric layer interposed therebetween.
7. The method for manufacturing the laminated ceramic capacitor according to claim 3 , wherein the conductive paste containing the Ni powder and the tin oxide powder which is represented by SnO or SnO 2 further contains a Ni—Sn alloy powder.
8. The method for manufacturing the laminated ceramic capacitor according to claim 7 , wherein the plurality of ceramic dielectric layers have a barium titanate-based perovskite compound as a main component thereof.
9. The method for manufacturing the laminated ceramic capacitor according to claim 7 , further comprising forming at least two external electrodes on an external surface of the ceramic laminated body, a first of the at least two external electrodes being in conduction with a first set of the plurality of internal electrodes, and a second of the at least two external electrodes being in conduction with a second set of the plurality of internal electrodes.
10. A method for manufacturing a laminated ceramic capacitor, the method comprising:
forming an unfired ceramic laminated body having a plurality of unfired ceramic dielectric layers and a plurality of unfired internal electrode patterns arranged along a plurality of interfaces between the unfired ceramic dielectric layers, the plurality of unfired internal electrode patterns being formed by applying a conductive paste containing a Ni—Sn alloy powder; and
firing the unfired ceramic laminated body to obtain a ceramic laminated body having a plurality of ceramic dielectric layers and a plurality of internal electrodes arranged along a plurality of interfaces between the ceramic dielectric layers,
wherein, after the firing, the Sn is dissolved in Ni in the internal electrodes, and a coefficient of variation value CV of a Sn/(Ni+Sn) ratio, which is represented by [{standard deviation of the Sn/(Ni+Sn) ratio}/{average value of the Sn/(Ni+Sn) ratio}]×100, is less than or equal to 32%, where the Sn/(Ni+Sn) ratio is a ratio of a content of a number of atoms of Sn to a total content of Sn and Ni in a region of each of the plurality of internal electrodes at a depth of 2 nm from a surface thereof facing a ceramic dielectric layer interposed therebetween.
11. The method for manufacturing the laminated ceramic capacitor according to claim 10 , wherein the plurality of ceramic dielectric layers have a barium titanate-based perovskite compound as a main component thereof.
12. The method for manufacturing the laminated ceramic capacitor according to claim 10 , further comprising forming at least two external electrodes on an external surface of the ceramic laminated body, a first of the at least two external electrodes being in conduction with a first set of the plurality of internal electrodes, and a second of the at least two external electrodes being in conduction with a second set of the plurality of internal electrodes.
13. The method for manufacturing the laminated ceramic capacitor according to claim 10 , wherein the conductive paste containing the Ni—Sn alloy powder further contains a tin oxide powder which is represented by SnO or SnO 2 and has a specific surface area of more than or equal to 10 m 2 /g as determined by a BET method.
14. The method for manufacturing the laminated ceramic capacitor according to claim 13 , wherein the plurality of ceramic dielectric layers have a barium titanate-based perovskite compound as a main component thereof.
15. The method for manufacturing the laminated ceramic capacitor according to claim 13 , further comprising forming at least two external electrodes on an external surface of the ceramic laminated body, a first of the at least two external electrodes being in conduction with a first set of the plurality of internal electrodes, and a second of the at least two external electrodes being in conduction with a second set of the plurality of internal electrodes.