Implementation of multi-tasking on a digital signal processor with a hardware stack
The present invention relates to the implementation for implementing multi-tasking on a digital signal processor. For that purpose blocking functions are arranged such that they do not make use of a processor's hardware stack. Respective function calls are replaced with a piece of inline assembly code, which instead performs a branch to the correct routine for carrying out said function. If a blocking condition of the blocking function is encountered, a task switch can be done to resume another task. While the hardware stack is not used when a task switch might have to occur, mixed-up contents of the hardware stack among function calls performed by different tasks are avoided.
1. An apparatus comprising:
a digital signal processor (DSP) with a hardware stack configured and arranged to be used by program code for call subroutines for which the hardware stack is invisible to a software program language used to program the DSP;
a first circuit configured and arranged to provide a set of DSP instructions including a primary set of instruction codes via the software program language and including inline assembly instruction codes;
the DSP being configured and arranged with the first circuit to execute the inline assembly instruction codes, and therein to
store a respective return address of a first task by saving a program counter for the digital signal processor,
branch to a different portion of the primary set of instruction codes for carrying out a blocking function, including maintaining the hardware stack so contents of the stack remain unmodified;
determine if a blocking condition for said blocking function is present;
store shared resources of the processor, if a blocking condition is determined;
switch to at least a second task; and
use the saved program counter to return to the first task.
2. The apparatus of claim 1 , wherein the DSP is configured and arranged with the first circuit to execute the inline assembly instruction codes, and therein to: re-check said blocking condition after switching back from said at least second task and, if said blocking condition is still present, switch to said at least second task.
3. The apparatus of claim 1 , wherein the DSP is configured and arranged with the first circuit to execute the inline assembly instruction codes, and therein to: if said blocking condition is no longer present, restore said shared resources, branch to said return address of said first task and continue execution of said first task.
4. The apparatus of claim 1 , wherein the DSP is configured and arranged with the first circuit to, if said blocking condition is not present, branch to said return address of said first task and continue execution of said first task.
5. The apparatus of claim 1 , wherein the hardware stack is configured and arranged to maintain the contents prior to and following the branching to the different portion of the primary set of instruction codes for carrying out the blocking function.
6. The apparatus of claim 1 , wherein the DSP is configured and arranged to store the shared resources of the processor by saving a state of registers of the DSP in memory.
7. The apparatus of claim 1 , wherein the DSP is configured and arranged with the first circuit to, in response to the blocking condition for the at least one subroutine being unsatisfied, branch to the respective return address of the first task.
8. The apparatus of claim 1 , wherein the DSP is configured and arranged with the first circuit to, in response to encountering a blocking condition in the execution of the second task, switch to resume execution of the first task.
9. The apparatus of claim 1 , wherein the first circuit is configured and arranged to provide at least one of the call subroutines as part of a set of DSP instructions that includes inline assembly codes.
10. An apparatus comprising:
a hardware stack configured and arranged to store call subroutines;
a storage circuit configured and arranged to store program instructions;
a processor circuit configured and arranged with the hardware stack and the storage circuit, to execute the program instructions for programming the processor circuit, independent from the execution of the call subroutines, and to
execute a first task of the program instructions on the processor circuit;
during the execution of the first task of the program instructions,
store a return address of the first task, and
branch to a subroutine for carrying out a blocking function while maintaining the hardware stack so contents of the stack remain unmodified;
in response to a blocking condition for the at least one subroutine being satisfied, perform a task switch to initiate execution of a second task; and
use the return address to task switch to resume execution of the first task.
11. The apparatus of claim 10 , wherein the processor circuit is configured and arranged to, after switching to resume execution of the first task:
in response to the blocking condition for the at least one subroutine being unsatisfied, branch to the return address of the first task; and
in response to the blocking condition for the at least one subroutine being satisfied, switch to execute a task that is different from the first task.
12. The apparatus of claim 10 , wherein the processor circuit is configured and arranged to, in response to a blocking condition for the at least one subroutine being satisfied, store values of shared resources of the processor including a set of registers of the processor.
13. The apparatus of claim 12 , wherein the processor circuit is configured and arranged to, if said blocking condition is no longer present after switching to resume execution of the first task, restore the shared resources to the stored values, branch to the return address, and continue execution of the first task.
14. An apparatus comprising:
a storage circuit configured and arranged to store at least one subroutine; and
a processor circuit configured and arranged with the storage circuit to
execute a first task in the processor circuit,
store a return address of the first task, including storing a program counter for the first task, in the storage circuit,
branch to one of the at least one subroutines for carrying out a blocking function,
in response to the blocking function for the subroutine being satisfied, initiate a second task,
after initiating the second task, use the stored program counter for the first task to return to the first task,
maintain the hardware stack so contents of the stack remain unmodified while branching to one of the at least one subroutines for carrying out a blocking function, and
use the stored program counter to return to the first task, in response to the second task satisfying a blocking condition.
15. The apparatus of claim 14 , wherein the processor circuit is configured and arranged with the storage circuit to carry out the blocking function using inline assembly code to store the return address of the first task and the program counter.
16. The apparatus of claim 14 , wherein the processor circuit is configured and arranged to execute the first task using a hardware stack, and to branch to the one of the at least one subroutines independently from the hardware stack while maintaining contents of the hardware stack pertaining to the first task.
17. The apparatus of claim 14 , wherein the processor circuit is configured and arranged to,
in response to a function corresponding to the first task being blocked, store the return address of the first task and the stored program counter, and initiate the second task, and
in response to a function corresponding to the second task being blocked, return to the first task using the stored return address and saved program counter.
18. The apparatus of claim 14 , wherein the processor circuit is configured and arranged to, in response to the second task satisfying a blocking condition:
returning from the second task and rechecking whether or not the blocking function for the subroutine is satisfied; and
switching to the second task if the blocking function for the subroutine is satisfied.
19. The apparatus of claim 14 , wherein the processor circuit is configured and arranged to, in response to the blocking function for the subroutine not being satisfied, using the stored program counter for the first task to return to the first task.