Systems and methods for managing read voltages in a cross-point memory array
Techniques are provided for managing voltages on memory cells in a cross-point array during a read operation. The techniques apply to vertical layer thyristor memory cells and non-thyristor memory cells. Voltages on selected bitlines (e.g., corresponding to memory cells from which data is to be read), are set to a read voltage level. Voltages on unselected bitlines (e.g., corresponding to memory cells from which data is not to be read and which are not to be disturbed) are set to a de-bias voltage level that is different from the read voltage level.
1. A method for accessing a memory cell in a cross-point memory array of memory cells, the method comprising:
setting voltages applied to a first plurality of electrically conducting lines to a standby voltage level;
changing a voltage applied to a first subset of a second plurality of electrically conducting lines from a first voltage level to a de-biased voltage level;
changing voltages applied to a subset of the first plurality of electrically conducting lines from the standby voltage level to a first read voltage level; and
subsequent to changing voltages applied to the subset of the first plurality of electrically conducting lines, detecting whether a voltage at each of a second subset of the second plurality of electrically conducting lines changes from the first voltage level to a second read voltage level.
2. The method of claim 1 , wherein the first plurality of electrically conducting lines are word-lines of the cross-point memory array.
3. The method of claim 1 , wherein the second plurality of electrically conducting lines are bit-lines of the cross-point memory array.
4. The method of claim 1 , wherein the subset of the first plurality of electrically conducting lines includes a word-line, the method comprising:
changing voltages applied to the subset of the first plurality of electrically conducting lines from the standby voltage level to the first read voltage level, subsequent to changing the voltage applied to the first subset of the second plurality of electrically conducting lines.
5. The method of claim 1 , further comprising:
selecting the first subset and the second subset of the second plurality of electrically conducting lines using a plurality of multiplexors, wherein each of the plurality of multiplexors is coupled to a respective electrically conducting line of the second plurality of electrically conducting lines.
6. The method of claim 1 , wherein the memory cells in the cross-point memory array comprise thyristor memory cells.
7. The method of claim 6 , wherein the first voltage level is a precharge voltage level, the method further comprising:
setting the voltage applied to the first subset of the second plurality of electrically conducting lines and the voltage applied to the second subset of the second plurality of electrically conducting lines to the precharge voltage level, prior to changing the voltage applied to the first subset of the second plurality of electrically conducting lines.
8. The method of claim 7 , wherein a voltage difference between the precharge voltage level and the standby voltage level is less than a latching voltage of the thyristor memory cells.
9. The method of claim 6 , wherein a voltage difference between the de-biased voltage level and the first read voltage level is less than a latching voltage of the thyristor memory cells.
10. The method of claim 6 , wherein a voltage difference between the second read voltage level and the first read voltage level is less than a latching voltage of the thyristor memory cells.
11. An apparatus for accessing a memory cell in a cross-point memory array of memory cells, the apparatus comprising:
a first plurality of driver circuitry configured to:
set voltages applied to a first plurality of electrically conducting lines to a standby voltage level; and
change voltages applied to a subset of the first plurality of electrically conducting lines from the standby voltage level to a first read voltage level;
a second plurality of driver circuitry configured to change a voltage applied to a first subset of a second plurality of electrically conducting lines from a first voltage level to a de-biased voltage level; and
a plurality of sense amplifier circuitry configured to detect whether a voltage at each electrically conducting line of a second subset of the second plurality of electrically conducting lines changes from the first voltage level to a second read voltage level, subsequent to the first plurality of driver circuitry changing voltages applied to the subset of the first plurality of electrically conducting lines.
12. The apparatus of claim 11 , wherein the first plurality of electrically conducting lines are word-lines of the cross-point memory array.
13. The apparatus of claim 11 , wherein the second plurality of electrically conducting lines are bit-lines of the cross-point memory array.
14. The apparatus of claim 11 , wherein the subset of the first plurality of electrically conducting lines includes a word-line, and wherein the first plurality of driver circuitry are configured to change the voltages applied to the subset of the first plurality of electrically conducting lines from the standby voltage level to the first read voltage level, subsequent to the second plurality of driver circuitry changing the voltage applied to the first subset of a second plurality of electrically conducting lines.
15. The apparatus of claim 11 , further comprising:
a plurality of multiplexors configured to select the first subset and the second subset of the second plurality of electrically conducting lines, wherein each of the plurality of multiplexors is coupled to a respective electrically conducting line of the second plurality of electrically conducting lines.
16. The apparatus of claim 11 , wherein the memory cells in the cross-point memory array comprise thyristor memory cells.
17. The apparatus of claim 16 , wherein the first voltage level is a precharge voltage level, and wherein the second plurality of driver circuitry is further configured to:
set the voltage applied to the first subset of the second plurality of electrically conducting lines and the voltage applied to the second subset of the second plurality of electrically conducting lines to the precharge voltage level, prior to changing the voltage applied to the first subset of the second plurality of electrically conducting lines.
18. The apparatus of claim 17 , wherein a voltage difference between the precharge voltage level and the standby voltage level is less than a latching voltage of the thyristor memory cells.
19. The apparatus of claim 16 , wherein a voltage difference between the de-biased voltage level and the first read voltage level is less than a latching voltage of the thyristor memory cells.
20. The apparatus of claim 16 , wherein a voltage difference between the second read voltage level and the first read voltage level is less than a latching voltage of the thyristor memory cells.