Semiconductor device

1. A semiconductor device comprising:

a plurality of conductive patterns formed on a semiconductor substrate, spaced apart from one another at a preset interval and extending in a first direction; and

a plurality of junction areas formed by doping impurities in the semiconductor substrate and provided between the conductive patterns,

wherein the plurality of junction areas include transistor junction areas and dummy junction areas,

wherein each of the transistor junction areas is connected through a contact to a source/drain electrode,

wherein each of the dummy junction areas is connected to a bias contact,

wherein the bias contact is formed at a higher level than the dummy junction areas,

wherein a well bias voltage is applied to the dummy junction areas through the bias contact,

wherein the plurality of the conductive patterns includes gate patterns fon ed between the transistor junction areas, connected to a gate electrode and configuring transistors together with the transistor junction areas,

wherein the transistors are connected to one another to configure at least one of an inverter, an NAND operator and an NOR operator,

wherein the substrate includes an active area and a dummy active area,

wherein the transistors are formed in the active area,

wherein the dummy junction areas are formed in the dummy active area,

wherein the plurality of the conductive patterns further comprise gate dummy patterns, and

wherein the gate dummy patterns are positioned in the dummy active area and are provided between the dummy junction areas, are in a floating state.

2. The semiconductor device of claim 1 ,

wherein the dummy junction area and the transistor junction area are doped with different conductive impurities.

3. The semiconductor device of claim 2 , further comprising:

a bias voltage pattern formed over the semiconductor substrate and providing the well bias voltage through the bias contact to the dummy junction area.

4. The semiconductor device of claim 3 ,

wherein the bias voltage pattern is formed at a level higher than the conductive patterns.

5. The semiconductor device of claim 1 , further comprising:

a dummy connection pattern extending in a second direction crossing the first direction and connecting the gate dummy patterns to one another.

6. A semiconductor device comprising:

logic array areas including transistors, wherein each of the transistors has an active area, a gate pattern, and a source and a drain, wherein the gate pattern is formed over the active area, wherein each of the source and the drain is adjacent to the gate pattern; and

a dummy area including a dummy active area and gate dummy patterns, wherein the dummy active area is formed between the logic array areas, wherein the gate dummy patterns are formed over the dummy active area, wherein each of the gate dummy patterns extends in a first direction, wherein the first direction substantially the same as a direction in which the gate pattern extends,

wherein a well bias voltage is applied to the dummy active area,

wherein the transistors are connected to one another to configure at least one of an inverter, an NAND operator and an NOR operator, and

wherein the gate dummy patterns are in a floating state.

7. The semiconductor device of claim 6 ,

wherein the dummy area includes a dummy junction area in the dummy active area, and

wherein the dummy junction area is doped with a conductivity different from the source and the drain.

8. The semiconductor device of claim 7 , further comprising:

a bias voltage pattern,

wherein the well bias voltage is provided to the bias voltage pattern through a bias contact, and

wherein the bias contact is formed in the dummy junction area.

9. The semiconductor device of claim 6 ,

wherein the gate pattern and the gate dummy patterns are extended with the same direction and arranged at substantially the same interval.

10. The semiconductor device of claim 6 , further comprising:

a dummy connection pattern that connects the gate dummy patterns to one another.

11. The semiconductor device of claim 6 , wherein the gate pattern included in the each of the transistors is connected to one another gate pattern included in the each of the transistors to configure a logic circuit.