IP Library Granted Patent US 9,842,959
Granted Patent B2
US 9,842,959 · App. 15/011,812 · Granted Dec 12, 2017

Method for producing a microsystem having pixels

Inventors: Carsten Giebeler (Edinburgh, GB); Neil Conway (Fife, GB)
Assignee: Pyreos, Ltd.
H01L31/1884G01J1/44G01J5/023G01J5/024G01J5/046G01J5/34H01L37/02H01L37/025G01J2005/345H01L41/316
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Quick Facts
Patent No.
US 9,842,959
App. No.
15/011,812
Granted
Dec 12, 2017
Kind
B2
Abstract

A Method for producing a microsystem ( 1 ) with pixels includes: producing a thermal silicon oxide layer on the surface of a silicon wafer as a base layer ( 5 ) by oxidation of the silicon wafer; producing a silicon oxide thin layer on the base layer as a carrier layer ( 6 )by thermal deposition; producing a platinum layer on the carrier layer by thermal deposition, whereby an intermediate product is produced; cooling the intermediate product to room temperature; pixel-like structuring of the platinum layer by removing surplus areas of the platinum layer, whereby bottom electrodes ( 8, 12 ) of the pixels ( 7, 8 ) are formed in pixel shape on the carrier layer in remaining areas; removing material on the side of the silicon wafer facing away from the base layer, so a frame ( 3 ) remains and a membrane ( 4 ) formed by the base layer and the carrier layer is spanned by the frame.

Claims (16)

1. A method for producing a microsystem with pixels, comprising:

providing a silicon wafer;

producing a thermal silicon oxide layer on the surface of the silicon wafer as a base layer with a thickness between 200 nm and 1000 nm by oxidation of the silicon wafer;

producing a silicon oxide thin layer directly on the base layer as a carrier layer with a thickness between 100 nm and 700 nm by a thermal deposition method;

producing a platinum layer directly on the carrier layer with a thermal deposition method with a thickness between 40 nm and 200 nm, whereby an intermediate product comprising the silicon wafer, the base layer, the carrier layer and the platinum layer is produced;

cooling the intermediate product to room temperature;

structuring the platinum layer with pixels by removing surplus areas of the platinum layer, whereby bottom electrodes of the pixels are formed in a pixel shape on the carrier layer in remaining areas;

removing material on a side of the silicon wafer facing away from the base layer, so that a frame remains and a membrane formed by the base layer and the carrier layer is spanned by the frame; and

finalizing of the microsystem.

2. The method according to claim 1 , wherein the platinum layer is sputtered between 300° C. and 550° C.

3. The method according to claim 1 , further comprising: producing a lead-zirconate-titanate layer directly on the platinum layer with a thermal deposition method and a thickness between 0.2 μm and 5 μm, whereby the intermediate product comprises the lead-zirconate-titanate layer.

4. The method according to claim 3 , wherein during the pixel structuring of the platinum layer, the lead-zirconate-titanate layer is simultaneously structured by removing surplus areas of the lead-zirconate-titanate layer, whereby lead-zirconate-titanate pixel parts of the pixels are formed on the bottom electrodes in remaining areas of the lead-zirconate-titanate layer.

5. The method according to claim 3 , further comprising: producing semi-transparent, electrically conductive electrode layer directly on the lead-zirconate-titanate layer with a thermal deposition method, whereby the intermediate product comprises the electrode layer.

6. The method according to claim 5 , wherein the electrode layer comprises platinum or a nickel-iron-compound or a nickel-chrome-compound.

7. The method according to claim 6 , wherein during the pixel structuring of the platinum layer and the lead-zirconate-titanate layer, the electrode layer is structured simultaneously by removing surplus areas of the second platinum layer, whereby head electrodes of the pixels are formed on the lead-zirconate-titanate pixel in remaining areas of the second platinum layer.

8. The method according to claim 1 , wherein the thermal deposition method is a sputter method.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 26, 2022
From: PYREOS LIMITED
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 059733/0972 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 13, 2016
From: GIEBELER, CARSTEN; CONWAY, NEIL
To: PYREOS LTD.
Reel/Frame 038264/0153 →
Priority Claims (1)
DE 10 2013 108 280 · Aug 1, 2013 · national
Continuity (2)
Continuation PCTEP2014066084 · Jul 25, 2014
Related Publication 20160149071A1 · May 26, 2016