Semiconductor structure and method of forming the same

1. A semiconductor structure, comprising a memory region, the memory region comprising:

an N th metal line;

a bottom via (BV) over the N th metal line, having a non-uniform lattice density at a top surface of the BV;

a recap layer directly covering only the BV, cutting off the non-uniform lattice density at the top surface of the BV;

a bottom electrode on the recap layer;

a magnetic tunneling junction (MTJ) layer on the bottom electrode, and the BV being directly under a projection of the MTJ layer;

a top electrode on the MTJ layer; and

an (N+1) th metal line over the top electrode.

2. The semiconductor structure of claim 1 , wherein the material of the recap layer is different from that of the bottom electrode.

3. The semiconductor structure of claim 1 , wherein the BV comprises TiN, TaN, or combinations thereof.

4. The semiconductor structure of claim 1 , wherein the bottom electrode comprises TiN, TaN, Ta, Ru, or combinations thereof.

5. The semiconductor structure of claim 1 , wherein the recap layer comprises TiN, TaN, W, Al, Ni, Co, Cu, or combinations thereof.

6. The semiconductor structure of claim 1 , wherein a roughness of the MTJ layer is less than 10 Å.

7. The semiconductor structure of claim 1 , wherein the recap layer comprises a thickness of at least 20 Å.

8. The semiconductor structure of claim 1 , further comprising a logic region adjacent to the memory region.

9. A magnetic random access memory (MRAM) structure, comprising:

an N th metal line;

a bottom via (BV) over the N th metal line, having a non-uniform lattice density over a top surface of the BV;

a recap layer directly covering only the BV, the recap layer comprising nitride materials;

a bottom electrode over the recap layer;

a magnetic tunneling junction (MTJ) layer on the bottom electrode, and the BV being directly under a projection of the MTJ layer;

a top electrode on the MTJ layer; and

an (N+1) th metal line over the top electrode.

10. The MRAM structure of claim 9 , further comprising a recap layer between the BV and the bottom electrode, the recap layer being configured to cut off the non-uniform lattice density at the top surface of the BV.

11. The MRAM structure of claim 10 , wherein the material of the recap layer is different from that of the BV.

12. The MRAM structure of claim 9 , wherein the BV comprises TiN, TaN or the combination thereof.

13. The MRAM structure of claim 10 , wherein the recap layer comprises a thickness in a range of from about 20 Å to about 50 Å.

14. The MRAM structure of claim 10 , wherein the recap layer comprises TiN, TaN, W, Al, Ni, Co or Cu.

15. A method for manufacturing a semiconductor structure, the method comprising:

forming a bottom via (BV) by a first deposition;

performing a chemical mechanical polishing (CMP) on a top surface of the BV;

forming a recap layer on the BV by a second deposition;

forming a magnetic tunneling junction (MTJ) layer over the recap layer and aligning with the underlying BV; and

patterning the MTJ layer and the recap layer by a mask layer;

wherein the first deposition comprises a TiN or TaN chemical vapor deposition (CVD) operation, thereby the top surface of the BV comprising a bulged surface as a result of a non-uniform lattice density.

16. The method of claim 15 , wherein the forming the recap layer comprises performing an atomic layer deposition (ALD) operation.

17. The method of claim 15 , wherein the forming the recap layer comprises performing a chemical vapor deposition (CVD) operation.

18. The method of claim 17 , after forming the recap layer, further comprising performing a CMP on a top surface of the recap layer.

19. The method of claim 15 , wherein a roughness of the MTJ layer is less than 10 Å.

20. The method of claim 15 , further comprising:

forming a bottom electrode on the recap layer; and

forming a top electrode over the MTJ layer.