IP Library › Granted Patent US 9,847,301
Granted Patent B2
US 9,847,301 · App. 15/448,015 · Granted Dec 19, 2017

Semiconductor device

Inventors: Toshifumi Minami (Yokohama, JP); Hiroyuki Maeda (Kawasaki, JP)
Assignee: TOSHIBA MEMORY CORPORATION
H01L23/562G01R31/2644H01L21/78H01L22/12H01L23/528H01L23/5226H01L23/585H01L27/11517H01L27/11563
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Quick Facts
Patent No.
US 9,847,301
App. No.
15/448,015
Granted
Dec 19, 2017
Kind
B2
Abstract

According to one embodiment, a semiconductor device includes a semiconductor substrate including an element region, a guard ring provided on an outer periphery of the element region and including a first interconnect and a first plug which electrically couples the first-interconnect and a first well region, a second interconnect provided above the first interconnect via a first insulating layer and non-electrically coupling to the first interconnect, and a first circuit coupled to the second interconnect. The first circuit detects one of a crack and a peeling of the guard ring in accordance with a break in the second interconnect or a short circuit between the second interconnect and the first interconnect.

Claims (37)

1. A semiconductor device comprising:

a semiconductor substrate including an element region having a semiconductor element;

a guard ring provided on an outer periphery of the element region and including a first interconnect and a first plug which electrically couples the first interconnect and a first well region, a ground voltage being applied to the guard ring;

a second interconnect provided above the first interconnect via a first insulating layer and non-electrically coupling to the first interconnect; and

a first circuit coupled to the second interconnect,

wherein the first circuit detects one of a crack and a peeling of the guard ring in accordance with a break in the second interconnect or a short circuit between the second interconnect and the first interconnect.

2. The device according to claim 1 , further comprising:

a third interconnect coupled to the first circuit; and

an electrode pad provided above the third interconnect via a second insulating layer and non-electrically coupling to the third interconnect,

wherein the first circuit detects one of a crack and a peeling of the electrode pad in accordance with a break of the third interconnect or a short circuit between the third interconnect and the electrode pad.

3. The device according to claim 1 , further comprising

a crack stopper provided on an outer periphery of the guard ring and including a fourth interconnect and a second plug which electrically couples the fourth interconnect and a second well region.

4. The device according to claim 1 , further comprising

an ammeter configured to measure a first current flowing in the second interconnect.

5. The device according to claim 1 , wherein

a first voltage different from the ground voltage is applied to the second interconnect when the one of the crack and the peeling of the guard ring is detected in the first circuit.

6. The device according to claim 2 , wherein

a first voltage different from the ground voltage is applied to the third interconnect when the one of the crack and the peeling in the electrode pad is detected in the first circuit.

7. The device according to claim 1 , wherein

the first circuit is one of an input-output circuit, a logic circuit, a voltage generator, and a controller.

8. The device according to claim 1 , wherein

if the second interconnect and the first interconnect are short-circuited, a first current higher than a second current flows in the second interconnect, and

if the second interconnect has the break, a fourth current lower than a third current which is lower than the second current flows in the second interconnect.

9. The device according to claim 2 , wherein

the first circuit and the electrode pad are coupled by a fifth interconnect different from the third Interconnect, and

if the third interconnect and the electrode pad are short-circuited, a first voltage applied to the third interconnect is input to the first circuit via the fifth interconnect.

10. The device according to claim 1 , wherein

the guard ring surrounds the outer periphery of the element region.

11. The device according to claim 1 , wherein

the crack stopper surrounds an outer periphery of the guard ring.

12. The device according to claim 1 , comprising a NAND flash memory.

13. The device according to claim 1 , wherein

the first interconnect surrounds the outer periphery of the element region.

14. The device according to claim 1 , wherein

the first plug has a shape of a line and surrounds the outer periphery of the element region.

15. The device according to claim 1 , wherein

the first circuit is provided in the element region.

Assignments (5)
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: K.K. PANGEA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 055669/0401 →
MERGER Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: K.K. PANGEA
Reel/Frame 055659/0471 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 055669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 26, 2017
From: KABUSHIKI KAISHA TOSHIBA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 043328/0388 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 2, 2017
From: MINAMI, TOSHIFUMI; MAEDA, HIROYUKI
To: KABUSHIKI KAISHA TOSHIBA
Reel/Frame 041444/0423 →
Priority Claims (1)
JP 2016-040287 · Mar 2, 2016 · national
Continuity (1)
Related Publication 20170256504A1 · Sep 7, 2017