IP Library Granted Patent US 9,847,363
Granted Patent B2
US 9,847,363 · App. 15/171,959 · Granted Dec 19, 2017

Semiconductor device with a radiation sensing region and method for forming the same

Inventors: Tsung-Han Tsai (Miaoli County, TW); Yun-Wei Cheng (Taipei, TW); Kuo-Cheng Lee (Tainan, TW); Chun-Hao Chou (Tainan, TW); Yung-Lung Hsu (Tainan, TW)
Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
H01L27/1463H01L27/1462H01L27/1464H01L27/14654H01L27/14685H01L27/14689H01L27/14636
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Quick Facts
Patent No.
US 9,847,363
App. No.
15/171,959
Granted
Dec 19, 2017
Kind
B2
Abstract

A semiconductor device includes a semiconductor substrate, a radiation-sensing region, at least one isolation structure, and a doped passivation layer. The radiation-sensing region is present in the semiconductor substrate. The isolation structure is present in the semiconductor substrate and adjacent to the radiation-sensing region. The doped passivation layer at least partially surrounds the isolation structure in a substantially conformal manner.

Claims (35)

1. A semiconductor device, comprising:

a semiconductor substrate;

a radiation-sensing region present in the semiconductor substrate; and

at least one isolation structure present in the semiconductor substrate and adjacent to the radiation-sensing region; and

a doped passivation layer at least partially surrounds the isolation structure in a substantially conformal manner, wherein the semiconductor substrate has a frontside and a backside, the radiation-sensing region is operable to detect a radiation wave that enters the semiconductor substrate through the backside of the semiconductor substrate, and the isolation structure extends from the backside of the semiconductor substrate to the frontside of the substrate.

2. The semiconductor device of claim 1 , wherein the doped passivation layer is further present at least partially in the backside of the semiconductor substrate.

3. The semiconductor device of claim 2 , wherein the doped passivation layer further substantially conforms to the backside of the semiconductor substrate.

4. The semiconductor device of claim 1 , wherein the radiation-sensing region comprises a first type dopant, and the doped passivation layer has a second dopant, and the second type dopant is of an opposite type to that of the first type dopant.

5. The semiconductor device of claim 1 , wherein the isolation structure includes a trench isolation structure.

6. The semiconductor device of claim 1 , wherein a cross-section area of the isolation structure adjacent to the backside of the semiconductor substrate is greater than a cross-section area of the isolation structure adjacent to the frontside of the semiconductor substrate.

7. A semiconductor device, comprising:

a semiconductor substrate having at least one trench therein;

a radiation-sensing region present in the semiconductor substrate;

at least one dielectric material present in the trench of the semiconductor substrate;

a doped passivation layer present at least in and at least substantially conforming to at least one sidewall of the trench; and

an interconnection structure present on a frontside of the semiconductor substrate, wherein the trench extends from a backside of the semiconductor substrate, wherein the doped passivation layer or the trench reaches the frontside of the semiconductor substrate.

8. The semiconductor device of claim 7 , wherein the doped passivation layer is further present at least partially in a backside of the semiconductor substrate.

9. The semiconductor device of claim 8 , wherein the doped passivation layer further substantially conforms to the backside of the semiconductor substrate.

10. The semiconductor device of claim 7 , wherein the radiation-sensing region comprises at least one of an N-type dopant and a P-type dopant, and the doped passivation layer comprises the other of the N-type dopant and the P-type dopant.

11. The semiconductor device of claim 7 , wherein the doped passivation layer is present at least in and at least substantially conforming to one bottom edge of the trench.

12. The semiconductor device of claim 7 , wherein the radiation-sensing region is surrounded by the dielectric material, and the doped passivation layer is present between the radiation-sensing region and the dielectric material.

13. The semiconductor device of claim 7 , wherein the trench narrows from a backside of the semiconductor substrate toward the radiation-sensing region.

14. A method for forming a semiconductor device, comprising:

forming at least one radiation-sensing region in a semiconductor substrate;

forming at least one trench in a backside of the semiconductor substrate and adjacent to the radiation-sensing region;

implanting a first dopant into the semiconductor substrate from the backside of the semiconductor substrate after the forming the trench; and

forming an interconnect structure on a frontside of the substrate, wherein at least a portion of the at least one trench is at least partially adjacent to the frontside of the substrate.

15. The method of claim 14 , further comprising:

filling the trench with a dielectric material.

16. The method of claim 14 , wherein the forming the radiation-sensing region comprises:

implanting a second dopant into the semiconductor substrate from a frontside of the semiconductor substrate, wherein the first dopant is of an opposite type to that of the second type dopant.

17. The semiconductor device of claim 1 , further comprising an interconnect structure present on the frontside.

18. The semiconductor device of claim 1 , wherein the semiconductor device is an image sensor.

19. The semiconductor device of claim 1 , wherein the at least one isolation structure narrows from a first side to a second side.

20. The method of claim 14 , wherein the forming the at least one trench forms the at least one trench to narrow from a first side to a second side.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 11, 2016
From: TSAI, TSUNG-HAN; CHENG, YUN-WEI; LEE, KUO-CHENG; CHOU, CHUN-HAO; HSU, YUNG-LUNG
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 039126/0921 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 30, 2016
From: TSAI, TSUNG-HAN; CHENG, YUN-WEI; LEE, KUO-CHENG; LEE, CHUN-HAO; HSU, YUNG-LUNG
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 039054/0179 →
Continuity (2)
Provisional Application 62243904 · Oct 20, 2015
Related Publication 20170110494A1 · Apr 20, 2017