Methods and apparatus for a multi-cycle time-based ADC

1. A multi-cycle time-based ADC configured to receive an analog input signal, comprising:

a first voltage-to-time converter configured to:

perform a first integration of the analog input signal during a first phase; and

a second voltage-to-time converter coupled in parallel with the first voltage-to-time converter and configured to perform a second integration of the analog input signal during a second phase;

wherein the ADC is configured to:

measure a length of time of the first integration;

measure a length of time of the second integration; and

sum the lengths of time to obtain a total integration time.

2. The multi-cycle time-based ADC according to claim 1 , wherein the first phase and the second phase are consecutive in time.

3. The multi-cycle time-based ADC according to claim 1 , further comprising an input switching circuit configured to selectively couple the analog input signal to the first and second voltage-to-time converters.

4. The multi-cycle time-based ADC according to claim 1 , further comprising a controller coupled to the first and second voltage-to-time converters, wherein the controller is configured to activate a sample-and-hold operation of the first and second time-to-voltage converters.

5. The multi-cycle time-based ADC according to claim 4 , further comprising a time-to-digital converter coupled to an output signal of the controller, wherein the time-to-digital converter is responsive to the output signal and measures the lengths of time of the first and second integration.

6. The multi-cycle time-based ADC according to claim 1 , wherein:

the first voltage-to-time converter is further configured to perform a sample-and-hold operation prior to the first phase; and

the second voltage-to-converter is further configured to perform a sample-and-hold operation during the first phase.

7. The multi-cycle time-based ADC according to claim 1 , wherein:

the first voltage-to-time converter comprises an first integrator circuit configured to perform the first integration; and

during the first integration, the first integrator circuit generates a first linearly decreasing output signal have a first rate of change.

8. The multi-cycle time-based ADC according to claim 7 , wherein:

the second voltage-to-time converter comprises a second integrator circuit configured to perform the second integration; and

during the second integration, the second integrator circuit generates a second linearly decreasing output signal have a second rate of change equal to the first rate of change.

9. The multi-cycle time-based ADC according to claim 1 , wherein

during the first integration, the first voltage-to-time converter generates a first linearly decreasing signal have a first rate of change;

during the second integration, the second voltage-to-time converter generates a second linearly decreasing signal have a second rate of change; and

the first rate of change is equal to the second rate of change.

10. A method for converting an analog signal into a digital signal, comprising:

performing a first integration operation of the analog input signal with a first voltage-to-time converter during a first phase;

measuring a length of time of the first integration operation;

sampling the analog input signal with a second voltage-to-time converter;

performing a second integration operation of the analog input signal with the second voltage-to-time converter during a second phase;

measuring a length of time of the second integration operation;

summing the lengths of time of the first and second integration operations to determine a total integration value;

converting the total integration value into a digital value.

11. The method according to claim 10 , wherein:

during the first integration operation, the first voltage-to-time converter generates a first linearly decreasing signal having a first rate of change; and

during the second integration operation, the second voltage-to-time converter generates a second linearly decreasing signal having a second rate of change equal to the first rate of change.

12. The method according to claim 10 , wherein the first phase and the second phase are consecutive in time.

13. The method according to claim 10 , further comprising sampling the analog input signal with the first voltage-to-time converter by selectively operating a first plurality of switches prior to the first phase.

14. The method according to claim 10 , further comprising sampling the analog signal with the second voltage-to-time converter by selectively operating a second plurality of switches during the first phase.

15. The method according to claim 10 , wherein:

measuring a length of time of the first integration operation comprises activating a start signal and a stop signal according to an output signal of the first voltage-to-time converter; and

measuring a length of time of the second integration operation comprises activating the start signal and the stop signal according to an output signal of the second voltage-to-time converter.

16. An ADC configured to receive an analog input signal, comprising:

a first voltage-to-time converter, configured to generate an first output signal, comprising:

a first integrator circuit configured to perform a first integration during a first phase, wherein the first integrator circuit generates a first integrator output signal;

a second voltage-to-time converter, coupled in parallel with the first voltage-to-time converter, comprising:

a second integrator circuit configured to perform a second integration during a second phase, wherein the second integrator circuit generates a second integrator output signal;

a controller coupled to the first and second voltage-to-time converters and responsive to the first and second output signals; and

a time-to-digital converter coupled to and responsive to the controller, wherein the time-to-digital converter is configured to:

measure a length of time of the first integration;

measure a length of time of the second integration; and

sum the lengths of time to obtain a total integration time.

17. The ADC according to claim 16 , wherein the first phase and the second phase are consecutive in time.

18. The ADC according to claim 16 , wherein the first and second integrator output signals have equal rates of change that decrease linearly.

19. The ADC according to claim 16 , wherein:

the first voltage-to-time converter is further configured to perform a sample-and-hold operation prior to the first phase; and

the second voltage-to-converter is further configured to perform a sample-and-hold operation during the first phase.

20. The ADC according to claim 16 , wherein:

each voltage-to-time converter cyclically performs integration and a sample-and-hold operation for a predetermined number of cycles; and

the cycles of the voltage-to-time converters are out of phase from each other.