Operation instruction generating circuit and consumable chip
An operation instruction generating circuit and a consumable chip. The operation instruction generating circuit includes: a power-on initialization module, connected to a signal wire and used for generating an initialization signal according to a signal transmitted by the signal wire; a middle signal generating module, connected to the power-on initialization module and the signal wire and used for combining, according to the initialization signal, the signal transmitted by the signal wire to generate a middle signal; and an instruction generating module, connected to the power-on initialization module and the middle signal generating module and used for generating an operation instruction according to the initialization signal and the middle signal or according to the initialization signal, the middle signal, and the signal transmitted by the signal wire. By the operation instruction generating circuit, the consumable chip is enabled to accurately respond to actions of a printing imaging device in time.
1. An operation instruction generating circuit, comprising:
a powering up and initializing module, connected to a signal line and configured to generate an initialized signal based on a signal transmitted through the signal line;
an intermediate signal generating module, connected to the powering up and initializing module and the signal line and configured to generate an intermediate signal based on the initialized signal in combination with the signal transmitted through the signal line; and
an instruction generating module, connected to the powering up and initializing module and the intermediate signal generating module and configured to generate an operation instruction based on the initialized signal and the intermediate signal or based on the initialized signal, the intermediate signal and the signal transmitted through the signal line.
2. The circuit according to claim 1 , wherein,
the intermediate signal is a high level signal or a low level signal, in a case that the signal transmitted through the signal line is a current source signal; or
the intermediate signal is a low level signal or a high level signal, in a case that the signal transmitted through the signal line is a voltage source signal.
3. The circuit according to claim 1 , wherein the powering up and initializing module comprises a first phase inverter and a first energy storage unit, an input terminal of the first phase inverter is connected to the signal line via a resistor, and the first energy storage unit is connected between the input terminal and a ground terminal of the first phase inverter.
4. The circuit according to claim 3 , wherein the first energy storage unit comprises a capacitor or a transistor.
5. The circuit according to claim 1 , wherein the intermediate signal generating module comprises a first signal generating unit, a latch and a second phase inverter, the latch is connected to the first signal generating unit and the powering up and initializing module, and the second phase inverter is connected to the latch.
6. The circuit according to claim 2 , wherein the intermediate signal generating module comprises a first signal generating unit, a latch and a second phase inverter, the latch is connected to the first signal generating unit and the powering up and initializing module, and the second phase inverter is connected to the latch.
7. The circuit according to claim 3 , wherein the intermediate signal generating module comprises a first signal generating unit, a latch and a second phase inverter, the latch is connected to the first signal generating unit and the powering up and initializing module, and the second phase inverter is connected to the latch.
8. The circuit according to claim 5 , wherein the first signal generating unit comprises:
a first switch, a control terminal of which is connected to the signal line via a first resistor and a first outreach terminal of which is connected to the signal line via a second resistor; and
a second switch, a control terminal of which is connected to an output terminal of the intermediate signal generating module, a first outreach terminal of which is connected to the control terminal of the first switch via a third resistor and a second outreach terminal of which is connected to a second outreach terminal of the first switch,
wherein a second energy storage unit is connected between the control terminal and the second outreach terminal of the first switch, and a third energy storage unit is connected between the first outreach terminal and the second outreach terminal of the first switch.
9. The circuit according to claim 8 , wherein,
a voltage of the third resistor is lower than a starting voltage of the first switch, in a case that the signal transmitted through the signal line is a current source signal; or
the voltage of the third resistor is higher than or equal to the starting voltage of the first switch, in a case that the signal transmitted through the signal line is a voltage source signal.
10. The circuit according to claim 1 , wherein the instruction generating module comprises:
a first AND gate, a first input terminal of which is connected to the signal line and a second input terminal of which is connected to the intermediate signal generating module; and/or
a first NOR gate and a second AND gate, wherein a first input terminal and a second input terminal of the first NOR gate are connected to the powering up and initializing module and the intermediate signal generating module respectively, and a first input terminal and a second input terminal of the second AND gate are connected to the signal line and the first NOR gate respectively.
11. The circuit according to claim 2 , wherein the instruction generating module comprises:
a first AND gate, a first input terminal of which is connected to the signal line and a second input terminal of which is connected to the intermediate signal generating module; and/or
a first NOR gate and a second AND gate, wherein a first input terminal and a second input terminal of the first NOR gate are connected to the powering up and initializing module and the intermediate signal generating module respectively, and a first input terminal and a second input terminal of the second AND gate are connected to the signal line and the first NOR gate respectively.
12. The circuit according to claim 3 , wherein the instruction generating module comprises:
a first AND gate, a first input terminal of which is connected to the signal line and a second input terminal of which is connected to the intermediate signal generating module; and/or
a first NOR gate and a second AND gate, wherein a first input terminal and a second input terminal of the first NOR gate are connected to the powering up and initializing module and the intermediate signal generating module respectively, and a first input terminal and a second input terminal of the second AND gate are connected to the signal line and the first NOR gate respectively.
13. A consumable chip, comprising:
an operation instruction generating circuit; and
a data storage circuit, configured to store data or output data in response to an operation instruction outputted by the operation instruction generating circuit,
wherein the operation instruction generating circuit comprises:
a powering up and initializing module, connected to a signal line and configured to generate an initialized signal based on a signal transmitted through the signal line;
an intermediate signal generating module, connected to the powering up and initializing module and the signal line and configured to generate an intermediate signal based on the initialized signal in combination with the signal transmitted through the signal line; and
an instruction generating module, connected to the powering up and initializing module and the intermediate signal generating module and configured to generate an operation instruction based on the initialized signal and the intermediate signal or based on the initialized signal, the intermediate signal and the signal transmitted through the signal line.
14. The consumable chip according to claim 13 , wherein
the intermediate signal is a high level signal or a low level signal, in a case that the signal transmitted through the signal line is a current source signal; or
the intermediate signal is a low level signal or a high level signal, in a case that the signal transmitted through the signal line is a voltage source signal.
15. The consumable chip according to claim 13 , wherein the powering up and initializing module comprises a first phase inverter and a first energy storage unit, an input terminal of the first phase inverter is connected to the signal line via a resistor, and the first energy storage unit is connected between the input terminal and a ground terminal of the first phase inverter.
16. The consumable chip according to claim 15 , wherein the first energy storage unit comprises a capacitor or a transistor.
17. The consumable chip according to claim 13 , wherein the intermediate signal generating module comprises a first signal generating unit, a latch and a second phase inverter, the latch is connected to the first signal generating unit and the powering up and initializing module, and the second phase inverter is connected to the latch.
18. The consumable chip according to claim 17 , wherein the first signal generating unit comprises:
a first switch, a control terminal of which is connected to the signal line via a first resistor and a first outreach terminal of which is connected to the signal line via a second resistor; and
a second switch, a control terminal of which is connected to an output terminal of the intermediate signal generating module, a first outreach terminal of which is connected to the control terminal of the first switch via a third resistor, and a second outreach terminal of which is connected to a second outreach terminal of the first switch,
wherein a second energy storage unit is connected between the control terminal and the second outreach terminal of the first switch, and a third energy storage unit is connected between the first outreach terminal and the second outreach terminal of the first switch.
19. The consumable chip according to claim 18 , wherein
a voltage of the third resistor is lower than a starting voltage of the first switch, in a case that the signal transmitted through the signal line is a current source signal; or
the voltage of the third resistor is higher than or equal to the starting voltage of the first switch, in a case that the signal transmitted through the signal line is a voltage source signal.
20. The consumable chip according to claim 13 , wherein the instruction generating module comprises:
a first AND gate, a first input terminal of which is connected to the signal line and a second input terminal of which is connected to the intermediate signal generating module; and/or
a first NOR gate and a second AND gate, wherein a first input terminal and a second input terminal of the first NOR gate are connected to the powering up and initializing module and the intermediate signal generating module respectively, and a first input terminal and a second input terminal of the second AND gate are connected to the signal line and the first NOR gate respectively.