IP Library Granted Patent US 9,865,513
Granted Patent B2
US 9,865,513 · App. 15/301,488 · Granted Jan 9, 2018

Semiconductor device manufacturing method

Inventors: Takuichiro Shitomi (Tokyo, JP); Kazuhisa Koga (Fukuoka, JP); Satoshi Rittaku (Tokyo, JP)
Assignee: Mitsubishi Electric Corporation
H01L22/12H01L21/02274H01L21/205H01L21/28008H01L21/3213H01L21/67248H01L21/76801
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Quick Facts
Patent No.
US 9,865,513
App. No.
15/301,488
Granted
Jan 9, 2018
Kind
B2
Abstract

A semiconductor device manufacturing method includes an element forming step of forming an element structure on a front surface of a substrate and forming a back structure on a back surface of the substrate, and a film forming step of performing film forming on a front surface of the element structure while measuring the temperature of the substrate by using a radiation thermometer that applies infrared rays of a wavelength λi to the back structure to obtain an infrared emissivity of the substrate. The back structure has a first layer exposed to the outside and a second layer in contact with the first layer, the refractive index of the second layer being smaller than that of the first layer, and the layer thickness of the first layer is set in a range from (2n−1)λi/8 to (2n+1)λi/8, with n being a positive even number.

Claims (19)

1. A semiconductor device manufacturing method, comprising:

an element forming step of forming an element structure on a front surface of a substrate and forming a back structure on a back surface of the substrate; and

a film forming step of performing film forming on a front surface of the element structure while measuring the temperature of the substrate by using a radiation thermometer that applies infrared rays of a wavelength λi to the back structure to obtain an infrared emissivity of the substrate,

wherein the back structure has a first layer exposed to the outside and a second layer in contact with the first layer, the refractive index of the second layer being smaller than that of the first layer, and

wherein in the film forming step, the layer thickness of the first layer is set in a range from (2n−1)λi/8 to (2n+1)λi/8, with n being a positive even number.

2. The semiconductor device manufacturing method according to claim 1 , wherein the element structure includes a transistor and a resistance element;

the back structure has a third layer between the second layer and the substrate;

the third layer is polysilicon formed at the time of film forming for a gate electrode of the transistor;

the second layer is a silicon oxide film formed at the time of film forming of an oxide film for patterning the gate electrode; and

the first layer is polysilicon formed at the time of film forming of a material for the resistance element.

3. The semiconductor device manufacturing method according to claim 1 , further comprising, as a step before the film forming step, a film thickness reducing step of reducing the layer thickness of the first layer so that the layer thickness of the first layer is in the range from (2n−1)λi/8 to (2n+1)λi/8, with n being a positive even number.

4. A semiconductor device manufacturing method, comprising:

an element forming step of forming an element structure on a front surface of a substrate and forming a back structure on a back surface of the substrate; and

a film forming step of performing film forming on a front surface of the element structure while measuring the temperature of the substrate by using a radiation thermometer that applies infrared rays of a wavelength λi to the back structure to obtain the infrared emissivity of the substrate,

wherein the back structure has a first layer exposed to the outside and a second layer in contact with the first layer, the refractive index of the second layer being larger than that of the first layer, and

wherein in the film forming step, the layer thickness of the first layer is set in a range from (2n−1)λi/8 to (2n+1)λi/8, with n being a positive odd number.

5. The semiconductor device manufacturing method according to claim 4 , further comprising, as a step before the film forming step, a film thickness reducing step of reducing the layer thickness of the first layer so that the layer thickness of the first layer is in the range from (2n−1)λi/8 to (2n+1)λi/8, with n being a positive odd number.

6. The semiconductor device manufacturing method according to claim 1 , wherein the element structure has a wiring layer, and

wherein, in the film forming step, an interlayer insulating film for the wiring layer is formed by high-density plasma CVD.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 1, 2020
From: MITSUBISHI ELECTRIC CORPORATION
To: ROHM CO., LTD.
Reel/Frame 054505/0493 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 3, 2016
From: SHITOMI, TAKUICHIRO; KOGA, KAZUHISA; RITTAKU, SATOSHI
To: MITSUBISHI ELECTRIC CORPORATION
Reel/Frame 039921/0843 →
Continuity (1)
Related Publication 20170040229A1 · Feb 9, 2017