IP Library Granted Patent US 9,865,641
Granted Patent B2
US 9,865,641 · App. 15/007,704 · Granted Jan 9, 2018

Solid-state imaging device, manufacturing method therefor, and imaging apparatus

Inventor: Yoshiaki Takemoto (Tokyo, JP)
Assignee: OLYMPUS CORPORATION
H01L27/14643H01L27/1464H01L27/1469H01L27/14632H01L27/14634H01L27/14636
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Quick Facts
Patent No.
US 9,865,641
App. No.
15/007,704
Granted
Jan 9, 2018
Kind
B2
Abstract

A solid-state imaging device includes: a first chip including a pixel array in which a plurality of photoelectric conversion portions converting incident light into an electric signal are disposed; a second chip having an area in a plan view less than an area of the first chip in the plan view and electrically and physically connected to the first chip; and a support portion provided to cover an entire region which is not covered with the second chip in a surface of the first chip connected to the second chip and configured to support the first chip so that flatness of the first chip may be maintained.

Claims (18)

1. A solid-state imaging device comprising:

a first chip including a pixel array in which a plurality of photoelectric conversion portions converting incident light into an electric signal are disposed, a thickness of the first chip being less than 10 micrometers;

a second chip having an area in a plan view less than an area of the first chip in the plan view, the second chip being physically connected to the first chip;

a connection portion disposed between the first chip and the second chip, the connection portion being configured to electrically connect the first chip and the second chip; and

a support portion provided to cover an entire region which is not covered with the second chip in a surface of the first chip connected to the second chip, the support portion being configured to support the first chip so as to maintain flatness of the first chip,

wherein the first chip includes a test terminal for external connection, and

the test terminal is provided at a position at which the test terminal does not overlap with the second chip in the plan view of the solid-state imaging device.

2. The solid-state imaging device according to claim 1 ,

wherein the support portion is formed of a resin or glass.

3. The solid-state imaging device according to claim 1 ,

wherein the support portion is disposed to surround a periphery of the second chip in the plan view of the solid-state imaging device.

4. The solid-state imaging device according to claim 1 ,

wherein a thickness of the support portion is greater than a thickness of the second chip, and

the second chip is covered with the support portion.

5. The solid-state imaging device according to claim 1 ,

wherein the first chip includes an input/output terminal for external connection, and

the input/output terminal is provided at a position at which the input/output terminal does not overlap with the second chip in the plan view of the solid-state imaging device.

6. An imaging apparatus comprising the solid-state imaging device according to claim 1 .

Assignments (2)
CHANGE OF ADDRESS Recorded Jun 20, 2017
From: OLYMPUS CORPORATION
To: OLYMPUS CORPORATION
Reel/Frame 042907/0078 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 27, 2016
From: TAKEMOTO, YOSHIAKI
To: OLYMPUS CORPORATION
Reel/Frame 037598/0450 →
Priority Claims (1)
JP 2013-168177 · Aug 13, 2013 · national
Continuity (2)
Continuation PCTJP2014063453 · May 21, 2014
Related Publication 20160141328A1 · May 19, 2016