IP Library Granted Patent US 9,867,282
Granted Patent B2
US 9,867,282 · App. 14/451,757 · Granted Jan 9, 2018

Circuit board with corner hollows

Inventors: Suming Hu (North York, CA); Neil McLellan (Austin, TX); Andrew K W Leung (Markham, CA); Jianguo Li (Scarborough, CA)
Assignees: ATI Technologies ULC; Advanced Micro Devices, Inc.
H05K1/0271H01L23/13H01L23/49838H05K3/0052H01L23/49816H01L2924/0002H01L2924/14H01L2924/3511H05K3/3442H05K2201/09027H05K2201/09154H05K2201/2009H05K2201/2018H05K2203/0228H05K2203/0746H05K2203/107Y10T29/49155
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Quick Facts
Patent No.
US 9,867,282
App. No.
14/451,757
Granted
Jan 9, 2018
Kind
B2
Abstract

A method of manufacturing is provided that includes singulating a circuit board from a substrate of plural of the circuit boards, wherein the circuit board is shaped to have four corner hollows. The corner hollows may be various shapes.

Claims (28)

1. An apparatus, comprising:

a circuit board having a first side configured to have a semiconductor chip mounted thereon and four corner hollows, the circuit board having a perimeter partially defined by the four corner hollows; and

wherein the circuit board includes an interconnect layer having plural conductor traces to conduct current and that track the perimeter.

2. The apparatus of claim 1 , wherein the corner hollows comprise concave shapes.

3. The apparatus of claim 1 , wherein the corner hollows comprise rectangular shapes.

4. The apparatus of claim 1 , comprising a semiconductor chip mounted on the first side of the circuit board.

5. The apparatus of claim 1 , comprising plural surface components mounted to the first side of the circuit board.

6. The apparatus of claim 1 , wherein the circuit board comprises a semiconductor chip package substrate.

7. The apparatus of claim 1 , wherein the circuit board has a hexagonal footprint.

8. The apparatus of claim 1 , wherein the circuit board comprises a plurality of outer edges and a second side opposite to the first side, the second side having a plurality of interconnect structures to electrically interface with another device, the interconnect structures located closest to the outer edges being connected to power or ground.

9. The apparatus of claim 1 , wherein the semiconductor chip package substrate comprises a core and plural build-up layers positioned on the core.

10. An apparatus, comprising:

a semiconductor chip package substrate having a first side, a second side opposite to the first side, four corner hollows and outer edges defined in part by the four corner hollows;

plural interconnect structures coupled to the second side to electrically interface with another device, those of the interconnect structures positioned closer to the edges than the other interconnect structures being operable to convey power and ground and the other interconnect structures being operable to convey signals; and

a semiconductor chip mounted on the first side.

11. The apparatus of claim 10 , wherein the corner hollows comprise concave shapes.

12. The apparatus of claim 10 , wherein the corner hollows comprise rectangular shapes.

13. The apparatus of claim 10 , comprising plural surface components mounted to the first side of the semiconductor chip package substrate.

14. The apparatus of claim 10 , wherein the semiconductor chip package substrate has a hexagonal footprint.

15. The apparatus of claim 10 , wherein the interconnect structures comprise solder balls.

16. The apparatus of claim 10 , wherein the interconnect structures comprise a land grid array.

17. The apparatus of claim 10 , wherein the circuit board comprises a core and plural build-up layers positioned on the core.

18. An apparatus, comprising:

a semiconductor chip package substrate having a first side and four corner hollows and a first footprint defined in part by the four corner hollows;

a semiconductor chip mounted on the first side; and

a stiffener frame mounted on the first side, the stiffener frame having a second footprint that tracks the first footprint.

19. The apparatus of claim 18 , wherein the stiffener frame includes an internal opening having a perimeter that tracks the second footprint.

20. The apparatus of claim 18 , wherein the semiconductor chip package substrate has a hexagonal footprint.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 5, 2014
From: HU, SUMING; LEUNG, ANDREW KW; LI, JIANGUO
To: ATI TECHNOLOGIES ULC
Reel/Frame 033465/0942 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 5, 2014
From: MCLELLAN, NEIL
To: ADVANCED MICRO DEVICES, INC.
Reel/Frame 033465/0963 →
Continuity (2)
Provisional Application 61866698 · Aug 16, 2013
Related Publication 20150049441A1 · Feb 19, 2015