Array substrate, its driving method, and display device
The present disclosure provides an array substrate including a plurality of subpixel array arranged in a matrix form. Each subpixel array may include a first subpixel, a second subpixel, a third subpixel, a first gate line for controlling the first subpixel, a second gate line for controlling the second subpixel, a third gate line for controlling the third subpixel, a first data line and a second data line. The first subpixel may be arranged between the first gate line and the second gate line. The second subpixel and the third subpixel may be arranged between the first gate line and the second gate line. The first subpixel, the second subpixel and the third subpixel may be arranged between the first data line and the second data line adjacent to each other. The first subpixel and the second subpixel may share the first data line, or the first subpixel and the third subpixel may share the second data line.
1. An array substrate, comprising a plurality of subpixel arrays arranged in a matrix form, each subpixel array comprising a first subpixel, a second subpixel, a third subpixel, a first gate line for controlling the first subpixel, a second gate line for controlling the second subpixel, a third gate line for controlling the third subpixel, a first data line and a second data line, wherein
the first subpixel is arranged between the first gate line and the second gate line,
the second subpixel and the third subpixel are arranged between the second gate line and the third gate line,
the first subpixel, the second subpixel and the third subpixel are arranged between the first data line and the second data line adjacent to each other, and
the first subpixel shares one of the first data line and the second data line with one of the second subpixel and the third subpixel,
wherein two adjacent subpixel arrays share at least one subpixel, and the shared at least one subpixel is a subpixel in both of the two adjacent subpixel arrays.
2. The array substrate according to claim 1 , wherein the second data line of the subpixel array is the same as the first data line of the adjacent subpixel array.
3. The array substrate according to claim 1 , wherein when the first subpixel and the second subpixel share the first data line, the first subpixel includes a first pixel electrode and a thin film transistor (TFT), a gate electrode of which is connected to the first gate line, a drain electrode of which is connected to the first data line, and a source electrode of which is connected to the first pixel electrode.
4. The array substrate according to claim 1 , wherein when the first subpixel and the second subpixel share the first data line, the second subpixel includes a second pixel electrode and a TFT, a gate electrode of which is connected to the second gate line, a drain electrode of which is connected to the first data line, and a source electrode of which is connected to the second pixel electrode.
5. The array substrate according to claim 1 , wherein when the first subpixel and the second subpixel share the first data line, the third subpixel includes a third pixel electrode and a TFT, a gate electrode of which is connected to the third gate line, a drain electrode of which is connected to the second data line, and a source electrode of which is connected to the third pixel electrode.
6. The array substrate according to claim 1 , wherein when the first subpixel and the third subpixel share the second data line, the first subpixel includes a first pixel electrode and a TFT, a gate electrode of which is connected to the first gate line, a drain electrode of which is connected to the second data line, and a source electrode of which is connected to the first pixel electrode.
7. The array substrate according to claim 1 , wherein when the first subpixel and the third subpixel share the second data line, the second subpixel includes a second pixel electrode and a TFT, a gate electrode of which is connected to the second gate line, a drain electrode of which is connected to the first data line, and a source electrode of which is connected to the second pixel electrode.
8. The array substrate according to claim 1 , wherein when the first subpixel and the third subpixel share the second data line, the third subpixel includes a third pixel electrode and a TFT, a gate electrode of which is connected to the third gate line, a drain electrode of which is connected to the second data line, and a source electrode of which is connected to the third pixel electrode.
9. The array substrate according to claim 1 , wherein the first subpixel, the second subpixel and the third subpixel are a red subpixel, a green subpixel and a blue subpixel, respectively.
10. The array substrate according to claim 1 , wherein the first subpixel, the second subpixel and the third subpixel are a green subpixel, a blue subpixel and a red subpixel, respectively.
11. The array substrate according to claim 1 , wherein the first subpixel, the second subpixel and the third subpixel are a blue subpixel, a red subpixel and a green subpixel, respectively.
12. A method for driving an array substrate which comprises a plurality of subpixel arrays arranged in a matrix form, each subpixel array comprising a first subpixel, a second subpixel, a third subpixel, a first gate line for controlling the first subpixel, a second gate line for controlling the second subpixel, a third gate line for controlling the third subpixel, a first data line and a second data line, wherein
the first subpixel is arranged between the first gate line and the second gate line,
the second subpixel and the third subpixel are arranged between the second gate line and the third gate line,
the first subpixel, the second subpixel and the third subpixel are arranged between the first data line and the second data line adjacent to each other, and
the first subpixel shares one of the first data line and the second data line with one of the second subpixel and the third subpixel,
wherein when the first subpixel and the second subpixel share the first data line, the method further comprises:
scanning progressively the first gate line, the second gate line and the third gate line of the subpixel array in an ith row;
scanning repeatedly the second gate line and the third gate line of the subpixel array in the ith row, and then scanning the first gate line of the subpixel array in an (i+1)th row;
scanning the first gate line, the second gate line and the third gate line of the subpixel array in the (i+1)th row;
scanning repeatedly the second gate line and the third gate line of the subpixel array in the (i+1)th row, and then scanning the first gate line of the subpixel array in an (i+2)th row; and
scanning the first gate line, the second gate line and the third gate line of the subpixel array in the (i+2)th row,
where 0<i<n, and both i and n are positive integers, or
when the first subpixel and the third subpixel share the second data line, the method further comprises:
scanning progressively the first gate line, the third gate line and the second gate line of the subpixel array in an ith row;
scanning repeatedly the third gate line and the second gate line of the subpixel array in the ith row, and then scanning the first gate line of the subpixel array in an (i+1)th row;
scanning the first gate line, the third gate line and the second gate line of the subpixel array in the (i+1)th row;
scanning repeatedly the third gate line and the second gate line of the subpixel array in the (i+1)th row, and then scanning the first gate line of the subpixel array in an (i+2)th row; and
scanning the first gate line, the third gate line and the second gate line of the subpixel array in the (i+2)th row,
where 0<i<n, and both i and n are positive integers.
13. The method according to claim 12 , wherein adjacent subpixel arrays share at least one subpixel.
14. A display device, comprising an array substrate, wherein the array substrate comprises a plurality of subpixel arrays arranged in a matrix form, each subpixel array comprising a first subpixel, a second subpixel, a third subpixel, a first gate line for controlling the first subpixel, a second gate line for controlling the second subpixel, a third gate line for controlling the third subpixel, a first data line and a second data line, wherein
the first subpixel is arranged between the first gate line and the second gate line,
the second subpixel and the third subpixel are arranged between the second gate line and the third gate line,
the first subpixel, the second subpixel and the third subpixel are arranged between the first data line and the second data line adjacent to each other, and
the first subpixel shares one of the first data line and the second data line with one of the second subpixel and the third subpixel,
wherein two adjacent subpixel arrays share at least one subpixel, and the shared at least one subpixel is a subpixel in both of the two adjacent subpixel arrays.
15. The display device according to claim 14 , wherein the second data line of the subpixel array is the same as the first data line of the adjacent subpixel array.
16. The display device according to claim 14 , wherein when the first subpixel and the second subpixel share the first data line, the first subpixel includes a first pixel electrode and a thin film transistor (TFT), a gate electrode of which is connected to the first gate line, a drain electrode of which is connected to the first data line, and a source electrode of which is connected to the first pixel electrode.
17. The display device according to claim 14 , wherein when the first subpixel and the second subpixel share the first data line, the second subpixel includes a second pixel electrode and a TFT, a gate electrode of which is connected to the second gate line, a drain electrode of which is connected to the first data line, and a source electrode of which is connected to the second pixel electrode.
18. The display device according to claim 14 , wherein when the first subpixel and the second subpixel share the first data line, the third subpixel includes a third pixel electrode and a TFT, a gate electrode of which is connected to the third gate line, a drain electrode of which is connected to the second data line, and a source electrode of which is connected to the third pixel electrode.
19. The display device according to claim 14 , wherein when the first subpixel and the third subpixel share the second data line, the first subpixel includes a first pixel electrode and a TFT, a gate electrode of which is connected to the first gate line, a drain electrode of which is connected to the second data line, and a source electrode of which is connected to the first pixel electrode.
20. The display device according to claim 14 , wherein when the first subpixel and the third subpixel share the second data line, the second subpixel includes a second pixel electrode and a TFT, a gate electrode of which is connected to the second gate line, a drain electrode of which is connected to the first data line, and a source electrode of which is connected to the second pixel electrode.
21. The display device according to claim 14 , wherein when the first subpixel and the third subpixel share the second data line, the third subpixel includes a third pixel electrode and a TFT, a gate electrode of which is connected to the third gate line, a drain electrode of which is connected to the second data line, and a source electrode of which is connected to the third pixel electrode.
22. The display device according to claim 14 , wherein the first subpixel, the second subpixel and the third subpixel are a red subpixel, a green subpixel and a blue subpixel, respectively; or
wherein the first subpixel, the second subpixel and the third subpixel are a green subpixel, a blue subpixel and a red subpixel, respectively; or
wherein the first subpixel, the second subpixel and the third subpixel are a blue subpixel, a red subpixel and a green subpixel, respectively.