IP Library Granted Patent US 9,876,167
Granted Patent B2
US 9,876,167 · App. 14/592,340 · Granted Jan 23, 2018

High yield RRAM cell with optimized film scheme

Inventors: Trinh Hai Dang (Hsinchu, TW); Hsing-Lien Lin (Hsin-Chu, TW); Cheng-Yuan Tsai (Chu-Pei, TW); Chin-Chieh Yang (New Taipei, TW); Yu-Wen Liao (New Taipei, TW); Wen-Ting Chu (Kaohsiung, TW); Chia-Shiung Tsai (Hsin-Chu, TW)
Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
H01L45/1233H01L45/08H01L45/12H01L45/146H01L45/1616H01L45/1641H01L45/1675
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Quick Facts
Patent No.
US 9,876,167
App. No.
14/592,340
Granted
Jan 23, 2018
Kind
B2
Abstract

The present disclosure relates to a method of forming a resistive random access memory (RRAM) cell having a good yield, and an associated apparatus. In some embodiments, the method is performed by forming a bottom electrode over a lower metal interconnect layer, and forming a variable resistance dielectric data storage layer having a first thickness onto the bottom electrode. A capping layer is formed onto the dielectric data storage layer. The capping layer has a second thickness that is in a range of between approximately 2 to approximately 3 times thicker than the first thickness. A top electrode is formed over the capping layer, and an upper metal interconnect layer is formed over the top electrode.

Claims (59)

1. A method of forming a resistive random access memory (RRAM) cell, comprising:

forming a bottom electrode over a lower metal interconnect layer;

forming a dielectric data storage layer having a first thickness onto the bottom electrode;

forming a capping layer onto the dielectric data storage layer, wherein the capping layer has a second thickness that is in a range of between approximately 2 to approximately 3 times thicker than the first thickness;

forming a top electrode over the capping layer; and

forming an upper metal interconnect layer over the top electrode, wherein the upper metal interconnect layer comprises an upper metal via contacting the top electrode at a location set back from sidewalls of the top electrode by a non-zero setback and an overlying upper metal wire that extends past opposing sidewalls of the upper metal via.

2. The method of claim 1 , wherein the first thickness of the dielectric data storage layer is in a range of between approximately 40 angstroms and approximately 60 angstroms.

3. The method of claim 1 , wherein the second thickness of the capping layer is in a range of between approximately 75 angstroms and approximately 150 angstroms.

4. The method of claim 1 , further comprising:

performing a retention bake after forming the dielectric data storage layer, wherein the retention bake is performed at a temperature in a range of between approximately 150° C. and approximately 250° C., for a time in a range of between approximately 24 hours and approximately 100 hours.

5. The method of claim 1 , wherein the dielectric data storage layer comprises one or more of: hafnium tantalum oxide (HfTaO), tantalum aluminum oxide (TaAlO), hafnium silicon oxide (HfSiO), and tantalum silicon oxide (TaSiO).

6. The method of claim 1 , wherein the dielectric data storage layer comprises hafnium aluminum oxide (HfAlO).

7. The method of claim 6 , wherein forming the dielectric data storage layer comprises:

performing a first plurality of atomic layer deposition (ALD) deposition cycles that respectively form a hafnium oxide (HfO) layer; and

performing a second plurality of ALD deposition cycles that respectively form an aluminum oxide (AlO) layer onto an underlying hafnium oxide (HfO) layer.

8. The method of claim 7 , wherein forming the HfO layer, comprises:

performing an first precursor gas pulse for a first pulse time to introduce water (H 2 O) into a processing chamber;

purging the processing chamber of the H 2 O;

performing a second precursor gas pulse for a second pulse time to introduce hafnium tetrachloride (HfCl 4 ) into the processing chamber, wherein the first pulse time is larger than the second pulse time; and

purging the processing chamber of the HfCl 4 .

9. The method of claim 8 , wherein the first pulse time has a duration in a range of between approximately 1000 milliseconds and approximately 2000 milliseconds.

10. The method of claim 1 , wherein the top electrode and the capping layer have sidewalls that are substantially aligned along a vertical line.

11. A method of forming a resistive random access memory (RRAM) cell, comprising:

depositing a bottom electrode layer over a lower metal interconnect layer;

depositing a dielectric data storage film onto the bottom electrode layer;

depositing a capping layer onto the dielectric data storage film;

depositing a top electrode layer onto the capping layer;

selectively patterning the top electrode layer and the capping layer to form a top electrode to have a first width;

selectively patterning the dielectric data storage film and the bottom electrode layer to form a bottom electrode to have a second width larger than the first width and to form a dielectric data storage layer having a first thickness over the bottom electrode, wherein the capping layer has a second thickness that is in a range of between approximately 2 to approximately 3 times thicker than the first thickness;

performing a retention bake after forming the dielectric data storage layer;

and

wherein the dielectric data storage layer and the bottom electrode have widths larger than the first width.

12. The method of claim 11 , wherein the dielectric data storage layer comprises a hafnium aluminum oxide (HfAlO) formed using an atomic layer deposition process, comprising:

performing a first plurality of atomic layer deposition (ALD) deposition cycles that respectively form a hafnium oxide (HfO) layer; and

performing a second plurality of ALD deposition cycles that respectively form an aluminum oxide (AlO) layer onto an underlying hafnium oxide (HfO) layer.

13. The method of claim 12 , wherein depositing the hafnium oxide (HfO) layer, comprises:

introducing a water (H 2 O) precursor into a processing chamber for a first pulse time to form a monolayer of H 2 O;

purging the H 2 O precursor from the processing chamber;

introducing a hafnium tetrachloride (HfCl 4 ) precursor in the processing chamber for a second pulse time that is two or more times shorter than the first pulse time, wherein the HfCl 4 precursor interacts with the monolayer of H 2 O to form the hafnium oxide (HfO) layer; and

purging the HfCl 4 precursor from the processing chamber.

14. The method of claim 11 , wherein the first thickness of the dielectric data storage layer is in a range of between approximately 40 angstroms and approximately 60 angstroms.

15. The method of claim 11 , wherein the second thickness of the capping layer is in a range of between approximately 75 angstroms and approximately 150 angstroms.

16. The method of claim 11 , wherein the retention bake is performed temporally between depositing the dielectric data storage layer and depositing the capping layer at a temperature in a range of between approximately 150° C. and approximately 250° C., for a time in a range of between approximately 24 hours and approximately 100 hours.

17. A method of forming a resistive random access memory (RRAM) cell, comprising:

forming a bottom electrode over a lower metal interconnect layer, by using a physical vapor deposition (PVD) process to form a lower portion of the bottom electrode and an in-situ plasma enhanced atomic layer deposition (PEALD) process to form an overlying upper portion of the bottom electrode;

forming a dielectric data storage layer having a first thickness, wherein the dielectric data storage layer comprises hafnium aluminum oxide, and

forming a capping layer onto the dielectric data storage layer, wherein the capping layer has a second thickness that is in a range of between approximately 2 to approximately 3 times thicker than the first thickness; and

forming a top electrode over the capping layer.

18. The method of claim 17 , wherein forming the dielectric data storage layer comprises:

introducing water into a processing chamber to form a first monolayer of water molecules;

purging the water from the processing chamber after forming the first monolayer of water molecules;

introducing hafnium tetrachloride into the processing chamber after purging the water, wherein the hafnium tetrachloride reacts with the first monolayer of water molecules to produce a monolayer of hafnium oxide;

purging the hafnium tetrachloride from the processing chamber after producing the monolayer of hafnium oxide;

introducing water into the processing chamber after purging the hafnium tetrachloride to form a second monolayer of water molecules over the monolayer of hafnium oxide;

purging the water from the processing chamber after forming the second monolayer of water molecules;

introducing Trimethylaluminum (TMA) into the processing chamber after purging the water, wherein the TMA reacts with the second monolayer of water molecules to produce a monolayer of aluminum oxide on the monolayer of hafnium oxide; and

purging the TMA from the processing chamber after producing the monolayer of aluminum oxide.

19. The method of claim 18 , wherein the water is introduced into the processing chamber using a first gas pulse having a first pulse time and the hafnium tetrachloride is introduced into the processing chamber using a second gas pulse having a second pulse time, wherein the second pulse time is shorter than the first pulse time.

20. The method of claim 17 , wherein the first thickness is in a first range of between approximately 40 angstroms and approximately 60 angstroms and the second thickness is in a second range of between approximately 75 angstroms and approximately 150 angstroms.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 8, 2015
From: DANG, TRINH HAI; LIN, HSING-LIEN; TSAI, CHENG-YUAN; YANG, CHIN-CHIEH; LIAO, YU-WEN; CHU, WEN-TING; TSAI, CHIA-SHIUNG
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 034665/0507 →
Continuity (2)
Continuation In Part 14242983 · Apr 2, 2014
Related Publication 20150287917A1 · Oct 8, 2015