IP Library › Granted Patent US 9,881,846
Granted Patent B2
US 9,881,846 · App. 15/254,508 · Granted Jan 30, 2018

Semiconductor device

Inventor: Takafumi Yamada (Matsumoto, JP)
Assignee: FUJI ELECTRIC CO., LTD.
H01L23/3121H01L23/24H01L23/3675H01L23/3735H01L23/4334H01L23/488H01L23/5386H01L25/072H01L27/0255H01L27/0647H01L23/36
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Quick Facts
Patent No.
US 9,881,846
App. No.
15/254,508
Granted
Jan 30, 2018
Kind
B2
Abstract

A semiconductor device includes: a semiconductor element; a laminated substrate including an insulating plate and a circuit board which is arranged on the front surface of the insulating plate and on which the semiconductor element is arranged; a lead terminal provided via solder in a major electrode of the front surface of the semiconductor element; and a sealing resin for sealing the semiconductor element, the laminated substrate, and the lead terminal, wherein a value of “Young's modulus of the sealing resin×(linear expansion coefficient of the lead terminal−linear expansion coefficient of the sealing resin)” is equal to or greater than −26×10 3 (Pa/° C.) and equal to or less than 50×10 3 (Pa/° C.).

Claims (28)

1. A semiconductor device, comprising:

a semiconductor element including a major electrode at a front surface of the semiconductor element;

a laminated substrate including

an insulating plate, and

a circuit board which is arranged on a front surface of the insulating plate, and on which the semiconductor element is arranged;

solder;

a lead terminal provided via the solder on the major electrode of the semiconductor element; and

a sealing resin for sealing the semiconductor element, the laminated substrate, and the lead terminal, a value of “a Young's modulus of the sealing resin×(a linear expansion coefficient of the lead terminal−a linear expansion coefficient of the sealing resin)” is equal to or greater than −26×10 3 (Pa/° C.) and equal to or less than 50×10 3 (Pa/° C.).

2. The semiconductor device according to claim 1 , wherein a value of “the Young's modulus of the sealing resin×(the linear expansion coefficient of the lead terminal−the linear expansion coefficient of the sealing resin)×a height of the sealing resin” is equal to or greater than −255×10 3 (Pa·mm/° C.) and equal to or less than 515×10 3 (Pa·mm/° C.).

3. The semiconductor device according to claim 2 , wherein the height of the sealing resin is equal to or greater than 6 mm and equal to or less than 11 mm.

4. The semiconductor device according to claim 1 , wherein a value of “the Young's modulus of the sealing resin×(the linear expansion coefficient of the lead terminal−the linear expansion coefficient of the sealing resin)×a height of the lead terminal” is equal to or greater than −93×10 3 (Pa·mm/° C.) and equal to or less than 159.5×10 3 (Pa·mm/° C.).

5. The semiconductor device according to claim 4 , wherein a height of the lead terminal along a direction to extend away from the semiconductor element is equal to or greater than 2 mm and equal to or less than 5 mm.

6. The semiconductor device according to claim 1 , wherein the Young's modulus of the sealing resin is equal to or greater than 5.1×10 9 Pa and equal to or less than 19.6×10 9 Pa, and the linear expansion coefficient of the sealing resin is equal to or greater than 7.5×10 −6 /° C. and equal to or less than 17.6×10 −6 /° C.

7. The semiconductor device according to claim 1 , wherein the lead terminal is made of copper.

8. The semiconductor device according to claim 1 , wherein the lead terminal includes a bonding section provided on the major electrode of the semiconductor element, and a step portion that vertically rises from the bonding section.

9. The semiconductor device according to claim 8 , wherein a corner portion of the bonding section of the lead terminal on a lower side of the step portion has a curvature.

10. The semiconductor device according to claim 8 , wherein

the major electrode of the semiconductor element includes a first area in which gate runners are provided, and a second area in which electrodes are provided, and

the lead terminal includes a corner portion where the bonding section and the step portion connect to each other, the corner portion being located on the second area.

11. A semiconductor device, comprising:

a semiconductor element including a major electrode at a front surface of the semiconductor element;

a laminated substrate including

an insulating plate, and

a circuit board which is arranged on a front surface of the insulating plate, and on which the semiconductor element is arranged;

solder;

a lead terminal provided via the solder on the major electrode of the semiconductor element; and

a sealing resin for sealing the semiconductor element, the laminated substrate, and the lead terminal, the sealing resin having predetermined ranges of a Young's modulus and a linear expansion coefficient so that a value of “a Young's modulus of the sealing resin×(a linear expansion coefficient of the lead terminal−a linear expansion coefficient of the sealing resin)” is in the range of −26×10 3 (Pa/° C.) to 50×10 3 (Pa/° C.), thereby reducing a plastic strain amplitude of the major electrode.

12. A semiconductor device, according to claim 11 , wherein the sealing resin has the Young's modulus in the range of 5.1×10 9 Pa to 19.6×10 9 Pa, and the linear expansion coefficient in the range of 7.5×10 −6 /° C. to 17.6×10 −6 /° C., so that the value of the Young's modulus of the sealing resin×(a linear expansion coefficient of the lead terminal−a linear expansion coefficient of the sealing resin) is in the range of −26×10 3 (Pa/° C.) to 50×10 3 (Pa/° C.), thereby reducing the plastic strain amplitude of the major electrode to a value equal to or less than 1.25%.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 1, 2016
From: YAMADA, TAKAFUMI
To: FUJI ELECTRIC CO., LTD.
Reel/Frame 039615/0771 →
Priority Claims (1)
JP 2015-209389 · Oct 23, 2015 · national
Continuity (1)
Related Publication 20170117201A1 · Apr 27, 2017