Transistor and electronic device
View Patent ↗A transistor capable of high-speed operation is provided. In a transistor including a back gate electrode, the back gate electrode is provided over a back gate wiring. A gate wiring and the back gate wiring are apart from each other; thus, the parasitic capacitance between the gate wiring and the back gate wiring is reduced and withstand voltage is improved. In addition, the width of the back gate electrode is smaller than a channel width; thus, the parasitic capacitance between the gate wiring and the back gate electrode is reduced and withstand voltage is improved.
1. A transistor comprising:
a first wiring;
a first electrode over the first wiring;
a first insulating layer over the first electrode;
a first semiconductor layer over the first insulating layer;
a second semiconductor layer over the first semiconductor layer;
a second electrode;
a third electrode;
a fourth electrode;
a second insulating layer;
a third insulating layer over the fourth electrode;
a third semiconductor layer;
a first layer; and
a second layer;
wherein the second semiconductor layer comprises a region overlapping with the second electrode and a region overlapping with the third electrode,
wherein the first layer comprises a region overlapping with the second electrode,
wherein the second layer comprises a region overlapping with the third electrode,
wherein the third semiconductor layer comprises a region overlapping with the first layer, a region overlapping with the second layer, and a region in contact with the second semiconductor layer,
wherein the fourth electrode comprises a region overlapping with the third semiconductor layer with the second insulating layer interposed therebetween,
wherein the third insulating layer is in contact with the second insulating layer,
wherein the first electrode comprises a region overlapping with a region where the third semiconductor layer is in contact with the second semiconductor layer,
wherein in a channel width direction, the second semiconductor layer comprises a first region overlapping with the first electrode, a second region not overlapping the first electrode, and a third region not overlapping the first electrode, and
wherein in the channel width direction, the first region is positioned between the second region and the third region.
2. The transistor according to claim 1 , wherein in the channel width direction, a difference between a width of the second region and a width of the third region is less than or equal to 20% of an average of the width of the second region and the width of the third region.
3. The transistor according to claim 1 , wherein a thickness of the first electrode is greater than or equal to a thickness of the first insulating layer and less than or equal to five times the thickness of the first insulating layer.
4. The transistor according to claim 1 , wherein the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer each comprise an oxide semiconductor.
5. The transistor according to claim 1 , wherein the first layer and the second layer each comprise an oxide semiconductor.
6. An electronic device comprising:
an antenna, a battery, an operation switch, a microphone, or a speaker, and
the transistor according to claim 1 .
7. A transistor comprising:
a first wiring;
a first gate electrode over the first wiring;
a first gate insulating layer over the first gate electrode;
a first semiconductor layer over the first gate insulating layer;
a second semiconductor layer over the first semiconductor layer;
a source electrode over the second semiconductor layer;
a drain electrode over the second semiconductor layer;
a first layer over the source electrode;
a second layer over the drain electrode;
a third semiconductor layer over the first layer, the second layer, and the second semiconductor layer;
a second gate insulating layer over the third semiconductor layer;
a second gate electrode over the second gate insulating layer; and
a third insulating layer over the second gate electrode,
wherein the source electrode and the drain electrode are electrically connected to the second semiconductor layer,
wherein the first layer overlaps with the source electrode,
wherein the second layer overlaps with the drain electrode,
wherein the third semiconductor layer is in contact with the second semiconductor layer between the first layer and the second layer,
wherein the fourth electrode overlaps with the third semiconductor layer with the second gate insulating layer interposed therebetween,
wherein the first gate electrode overlaps with a region where the third semiconductor layer is in contact with the second semiconductor layer,
wherein in a channel width direction, the second semiconductor layer comprises a first region overlapping with the first gate electrode, a second region not overlapping the first gate electrode, and a third region not overlapping the first gate electrode, and
wherein in the channel width direction, the first region is positioned between the second region and the third region.
8. The transistor according to claim 7 , wherein in the channel width direction, a difference between a width of the second region and a width of the third region is less than or equal to 20% of an average of the width of the second region and the width of the third region.
9. The transistor according to claim 7 , wherein a thickness of the first gate electrode is greater than or equal to a thickness of the first gate insulating layer and less than or equal to five times the thickness of the first gate insulating layer.
10. The transistor according to claim 7 , wherein the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer each comprise an oxide semiconductor.
11. The transistor according to claim 7 , wherein the first layer and the second layer each comprise an oxide semiconductor.
12. An electronic device comprising:
an antenna, a battery, an operation switch, a microphone, or a speaker, and
the transistor according to claim 7 .