Gallium beam lithography for superconductive structure formation
The present invention relates to the use of gallium beam lithography to form superconductive structures. Generally, the method includes exposing a surface to gallium to form an implanted region and then removing material adjacent to and/or below that implanted region. In particular embodiments, the methods herein provide microstructures and nanostructures in any useful substrate, such as those including niobium, tantalum, tungsten, or titanium.
1. A method comprising:
exposing a region of a surface of a substrate with a focused ion beam of gallium so as to define an implanted region, wherein the implanted region comprises a superconductive region of niobium, tantalum, tungsten, and/or titanium nitride; and
removing material from regions laterally adjacent to and below the implanted superconductive region by subtractive etching, the subtractive etching being a two-phase process including
a first phase of anisotropic etching for removing non-implanted material laterally adjacent to the implanted superconductive region to define a superconductive structure; and
a second phase of isotropic etching for removing non-implanted material below the implanted superconductive region, thereby releasing the superconductive structure so as to be held in suspension over the substrate.
2. The method of claim 1 , wherein the surface, or a portion thereof, comprises a layer of metal or a metal compound deposited on the substrate.
3. The method of claim 2 , wherein the metal or metal compound is selected from the group consisting of niobium, niobium nitride, niobium silicide, niobium silicon nitride, niobium aluminum nitride, niobium oxide, niobium titanium, niobium titanium nitride, titanium nitride, tantalum, tantalum oxide, tantalum nitride, and alloys thereof.
4. The method of claim 1 , wherein the subtractive etching is performed by a dry etching process.
5. The method of claim 4 , wherein the subtractive etching process is performed within a temperature range of about 25° C. to about 400° C.
6. The method of claim 5 , wherein the subtractive etching process is performed under conditions including a low pressure less than about 20 mTorr.
7. The method of claim 5 , wherein the subtractive etching process is performed in the presence of an etchant and a passivation agent.
8. The method of claim 5 , wherein the subtractive etching process is performed by a fluorine-based inductively coupled plasma reactive ion etch.
9. The method of claim 8 , wherein the fluorine-based inductively coupled plasma reactive ion etch is performed, at least in part, in a continuous phase using an etchant and a passivation agent.
10. The method of claim 9 , wherein the etchant is one or more species selected from the group consisting of SF 6 , F 2 , XeF 3 , NF 3 , BF 3 , HCl, and HF; and the passivation agent is one or more species selected from the group consisting of CF 4 , C 2 F 2 , C 2 F 4 , C 2 F 6 , C 3 F 5 , C 4 F 8 , C 4 F 6 , C 5 F 8 , CHF 3 , CH 2 F 2 , CH 3 F, C 2 H 2 F 2 , and O 2 .
11. The method of claim 10 , wherein the etchant further comprises one, two, or all three species selected from the group consisting of argon, nitrogen, and oxygen.
12. The method of claim 1 , wherein the exposing step comprises rastering the focused ion beam over the region.
13. The method of claim 1 , wherein the focused ion beam comprises a voltage less than about 50 keV.
14. The method of claim 1 , wherein the first phase is performed using sulfur hexafluoride (SF 6 ) as an etchant combined with octafluorocyclobutane (C 4 F 8 ) as a passivation agent; and the second phase is performed using sulfur hexafluoride (SF 6 ) as the etchant without C 4 F 8 passivation.
15. The method of claim 1 , further comprising, prior to the exposing step, depositing a film comprises niobium, tantalum, tungsten, and/or titanium nitride on the substrate, thereby providing the film as a surface for the exposing step.
16. The method of claim 1 , further comprising, after the removing step, eliminating a gallium-rich portion of the implanted region.
17. The method of claim 1 , wherein the method is performed as a back-end-of-line (BEOL) process, after a CMOS process flow is used to fabricate one or more integrated circuits on the substrate.