Protocol for memory power-mode control
In one embodiment, a memory device includes a memory core and input receivers to receive commands and data. The memory device also includes a register to store a value that indicates whether a subset of the input receivers are powered down in response to a control signal. A memory controller transmits commands and data to the memory device. The memory controller also transmits the value to indicate whether a subset of the input receivers of the memory device are powered down in response to the control signal. In addition, in response to a self-fresh command, the memory device defers entry into a self-refresh operation until receipt of the control signal that is received after receiving the self-refresh command.
1. A method of operating a memory controller, the method comprising:
transmitting commands and data to a plurality of receivers of a memory device via a first interface of the memory controller, the plurality of receivers including a first set of receivers that receive the commands and a second set of receivers that receive the data;
transmitting a value to the memory device that indicates the second set of receivers of the memory device that are to be powered down via a second interface of the memory controller;
transmitting a control signal to the memory device to power down the second set of receivers of the memory device indicated by the value via the second interface of the memory controller; and
transmitting, via the first interface, a command that is received by the first set of receivers while the second set of receivers are powered down.
2. The method of claim 1 , wherein the second interface is operated at a lower operating frequency than the first interface.
3. The method of claim 1 , wherein in response to the control signal both the first set of receivers and the second set of receivers are powered down.
4. The method of claim 1 , wherein the value transmitted to the memory device further indicates a subset of transmitters of the memory device that are to be powered down in response to the control signal.
5. The method of claim 4 , further comprising:
powering down a subset of receivers of the memory controller that are connected to the subset of transmitters of the memory device responsive to the subset of the transmitters of the transmitter being powered down.
6. The method of claim 1 , further comprising:
providing, via the first interface, a self-refresh command to the memory device prior to transmitting the control signal, and
wherein the memory device defers entry into a self-refresh operation responsive to the self-refresh command until the control signal is received.
7. The method of claim 6 , further comprising:
while the memory device is performing the self-refresh operation, transmitting a control signal to the memory device for the subset of the receivers to power on via the second interface;
transmitting, via the first interface, calibration commands to the memory device responsive to the subset of the receivers being powered on, the calibration commands for calibrating the subset of the receivers; and
transmitting, via the second interface, the control signal for the subset of the receivers of the memory device to power down responsive to completion of the calibration of the subset of the receivers.
8. A memory controller comprising:
a first interface to transmit commands and data to a plurality of receivers of a memory device, the plurality of receivers including a first set of receivers that receive the commands and a second set of receivers that receive the data;
a second interface to transmit a value to the memory device that indicates the second set of receivers of the memory device that are to be powered down and to transmit a control signal to the memory device to power down the second set of receivers of the memory device indicated by the value; and
wherein the first interface is further configured to transmit a command that is received by the first set of receivers while the second set of receivers are powered down.
9. The memory controller of claim 8 , wherein the second interface operates at a lower operating frequency than the first interface.
10. The memory controller of claim 8 ,
wherein in response to the control signal both the first set of receivers and the second set of receivers are powered down.
11. The memory controller of claim 8 , wherein the value transmitted to the memory device further indicates a subset of transmitters of the memory device that are to be powered down in response to the control signal.
12. The memory controller of claim 11 , further comprising:
a plurality of receivers that receive data from the subset of transmitters of the memory device;
wherein the plurality of receivers of the memory controller are powered down responsive to the subset of the transmitters of the memory device being powered down.
13. The memory controller of claim 8 , wherein the first interface is configured to provide to the memory device a self-refresh command prior to transmitting the control signal, and
wherein the memory device defers entry into a self-refresh operation responsive to the self-refresh command until the control signal is received.
14. The memory controller of claim 13 , wherein while the memory device is performing the self-refresh operation, the second interface is further configured to transmit a control signal to the memory device for the subset of the receivers to power on;
wherein the first interface is configured to transmit calibration commands to calibrate the subset of the receivers responsive to the subset of the receivers being powered on; and
wherein the second interface is configured to transmit the control signal for the subset of the receivers of the memory device to power down responsive to completion of the calibration of the subset of the receivers.
15. The memory controller of claim 8 , wherein the first interface and the second interface are part of a single interface of the memory controller.
16. A memory controller comprising:
means for transmitting commands and data to a plurality of receivers of a memory device, the plurality of receivers including a first set of receivers that receive the commands and a second set of receivers that receive the data; and
means for transmitting a value to the memory device that indicates at least the second set of receivers of the memory device that are powered down and for transmitting a control signal to the memory device to power down the second set of receivers of the memory device indicated by the value; and
wherein the means for transmitting the commands and data is further for transmitting a command that is received by the first set of receivers while the second set of receivers are powered down.
17. The memory controller of claim 16 , wherein the means for transmitting the value operates at a lower operating frequency than the means for transmitting commands.