IP Library Granted Patent US 9,887,633
Granted Patent B2
US 9,887,633 · App. 14/616,987 · Granted Feb 6, 2018

Resonant converter control techniques to manage negative SR current

Inventor: Hang-Seok Choi (Bedford, NH)
Assignee: Fairchild Semiconductor Corporation
H02M3/33592H02M3/33569H02M2001/0058Y02B70/1433Y02B70/1475Y02B70/1491Y02P80/112
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Quick Facts
Patent No.
US 9,887,633
App. No.
14/616,987
Granted
Feb 6, 2018
Kind
B2
Abstract

This disclosure provides control techniques for a resonant converter. In one embodiment, a resonant converter controller includes predictive gate drive circuitry configured to generate a predictive gate drive signal indicative of a time duration from a rising edge of a first drive signal for controlling a conduction state of a first inverter switch of a resonant converter system to a synchronous rectifier (SR) current zero crossing instant of a first SR switch of the resonant converter system, wherein the first tracking signal is based on at least the first drive signal and a voltage drop across the first SR switch. The resonant converter controller may also include SR gate drive shrink circuitry configured to generate an SR gate drive turn on delay signal to increase delay of SR on times in response to detection of a decrease in load current demand of the resonant converter system.

Claims (39)

1. A resonant converter system, comprising:

transformer circuitry including a primary side and a secondary side;

first stage circuitry coupled to said primary side, said first stage circuitry including inverter circuitry having a first inverter switch, a second inverter switch and resonant tank circuitry;

pulse frequency modulation (PFM) controller circuitry configured to generate a first drive signal and a second drive signal to control on and off times of said first and second inverter switches, respectively;

second stage circuitry coupled to said secondary side, said second stage circuitry including synchronous rectifier (SR) circuitry having a first SR switch and a second SR switch corresponding to said first and second inverter switches, respectively; and

SR controller circuitry configured to generate control signals to control said on and off times of said first and second SR switches, respectively, based on at least said first and second drive signals, to detect a decrease in a load current demand of said resonant converter system, and to increase delay of said on times in response to detection of the decrease in load current demand of said resonant converter system.

2. The resonant converter system of claim 1 , further comprising an integration circuit configured to convert measured current through said second inverter switch to a voltage.

3. The resonant converter system of claim 2 , further comprising a peak detect circuit configured to detect a peak of said converted measured current for estimation of said load current demand.

4. The resonant converter system of claim 3 , wherein said SR controller circuitry is further configured to generate a gate drive turn on delay signal based on a difference between said detected peak voltage and a threshold voltage, said threshold voltage representing a percentage of a full power load of said resonant converter.

5. The resonant converter system of claim 4 , wherein said SR controller circuitry is further configured to generate a predictive gate drive signal for each SR switch, said predictive gate drive signal having a time duration from approximately a rising edge of said drive signal of the corresponding inverter switch to an SR current zero crossing instant of said SR switch.

6. The resonant converter system of claim 5 , wherein said SR controller circuitry is further configured to turn off each SR switch based at least on a result of a logical AND of said predictive gate drive signal and said gate drive turn on delay signal.

7. The resonant converter system of claim 1 , wherein said increased delay of said on times, in response to detection of a decrease in load current demand, prevents negative current flow through said SR switches.

8. The resonant converter system of claim 1 , wherein said PFM controller circuitry is further configured to generate said first and second drive signals using feedback based at least on an output voltage of said resonant converter circuitry.

9. A resonant converter controller, comprising:

predictive gate drive circuitry configured to generate a predictive gate drive signal indicative of a time duration from a rising edge of a first drive signal for controlling a conduction state of a first inverter switch of a resonant converter system to a synchronous rectifier (SR) current zero crossing instant of a first SR switch of said resonant converter system, wherein a first tracking signal is based on at least said first drive signal and a voltage drop across said first SR switch; and

SR gate drive shrink circuitry configured to detect a decrease in load current demand of said resonant converter system, and to generate an SR gate drive turn on delay signal to increase delay of SR on times in response to detection of the decrease in load current demand of said resonant converter system.

10. The resonant converter controller of claim 9 , wherein said predictive gate drive circuitry comprises at least an analog comparator, a first edge-triggered flip-flop, a counter, a register, an inverter, a digital comparator, and a second edge-triggered flip-flop.

11. The resonant converter controller of claim 9 , wherein said SR gate drive shrink circuitry comprises at least an analog subtraction circuit, a counter, an analog to digital converter, and a digital comparator.

12. The resonant converter controller of claim 9 , further comprising an integration circuit configured to convert measured current through a second inverter switch to a voltage.

13. The resonant converter controller of claim 12 , further comprising a peak detect circuit configured to detect a peak of said converted measured current for estimation of said load current demand.

14. The resonant converter controller of claim 13 , wherein said SR gate drive shrink circuitry is further configured to generate said gate drive turn on delay signal based on a difference between said detected peak voltage and a threshold voltage, said threshold voltage representing a percentage of a full power load of said resonant converter.

15. The resonant converter controller of claim 9 , further comprising logic circuitry including at least a logical AND configured to receive said predictive gate drive signal and said gate drive turn on delay signal and generate a control signal for said first SR switch.

16. A method comprising:

generating first and second drive signals to control on and off times of first and second inverter switches, respectively, in a first stage of a resonant converter system;

determining voltage drops across each of first and second synchronous rectifier (SR) switches in a second stage of said resonant converter system, said first and second SR switches corresponding to said first and second inverter switches, respectively;

generating control signals to control on and off times of said first and second SR switches, respectively, based on at least said first and second drive signals and voltage drops across said first and second SR switches;

detecting a decrease in load current demand of said resonant converter system; and

increasing delay of said on times in response to said detection of the decrease in load current of said resonant converter system.

17. The method of claim 16 , further comprising:

measuring current through said second inverter switch, converting said measured current to a voltage based on integration of said measured current and estimating said load current demand based on a detected peak of said voltage.

18. The method of claim 17 , further comprising:

generating a gate drive turn on delay signal based on a difference between said detected peak voltage and a threshold voltage, said threshold voltage representing a percentage of a full power load of said resonant converter.

19. The method of claim 18 , further comprising:

generating a predictive gate drive signal for each SR switch, said predictive gate drive signal having a time duration from approximately a rising edge of said drive signal of the corresponding inverter switch to an SR current zero crossing instant of said SR switch.

20. The method of claim 19 , further comprising:

turning off each SR switch based at least on a result of a logical AND of said predictive gate drive signal and said gate drive turn on delay signal.

21. The method of claim 16 , wherein said increased delay of said on times, in response to detection of a decrease in load current demand, prevents negative current flow through said SR switches.

22. The method of claim 16 , further comprising:

generating said first and second drive signals using feedback based at least on an output voltage of said resonant converter circuitry.

Assignments (7)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 058871, FRAME 0799 Recorded Jun 23, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 065653/0001 →
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 040075, FRAME 0644 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064070/0536 →
SECURITY INTEREST Recorded Nov 12, 2021
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 058871/0799 →
RELEASE OF SECURITY INTEREST Recorded Oct 28, 2021
From: DEUTSCHE BANK AG NEW YORK BRANCH
To: FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 057969/0206 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 3, 2021
From: FAIRCHILD SEMICONDUCTOR CORPORATION
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 057694/0374 →
PATENT SECURITY AGREEMENT Recorded Sep 19, 2016
From: FAIRCHILD SEMICONDUCTOR CORPORATION
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 040075/0644 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 9, 2015
From: CHOI, HANG-SEOK
To: FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 034917/0511 →
Continuity (2)
Provisional Application 61938443 · Feb 11, 2014
Related Publication 20150229219A1 · Aug 13, 2015