Semiconductor device and method
A method and device are provided wherein a first semiconductor device and a via are encapsulated with an encapsulant. A redistribution layer connects the first semiconductor device to a second semiconductor device. In a particular embodiment the first semiconductor device is an integrated voltage regulator and the second semiconductor device is a logic device such as a central processing unit.
1. A semiconductor device comprising:
a first semiconductor device, wherein the first semiconductor device comprises a first voltage regulator;
an encapsulant encapsulating the first semiconductor device;
a through via separated from the first semiconductor device and extending from a first side of the encapsulant to a second side of the encapsulant;
a first redistribution layer electrically connected to the through via on a first side of the encapsulant;
a second semiconductor device electrically connected to the first semiconductor device through the first redistribution layer, wherein the second semiconductor device comprises a first logic device; and
a third semiconductor device, wherein the encapsulant encapsulates the third semiconductor device and wherein the third semiconductor device comprises a second voltage regulator.
2. The semiconductor device of claim 1 , further comprising a fourth semiconductor device electrically connected to the first redistribution layer and located on an opposite side of the first redistribution layer than the third semiconductor device, the fourth semiconductor device comprising a second logic device.
3. The semiconductor device of claim 2 , further comprising:
a fifth semiconductor device electrically connected to the first redistribution layer and located on an opposite side of the first redistribution layer than the third semiconductor device, the fifth semiconductor device comprising an I/O device; and
a second encapsulant encapsulating the second semiconductor device, the fourth semiconductor device, and the fifth semiconductor device.
4. The semiconductor device of claim 1 , wherein the first semiconductor device comprises a through silicon via.
5. The semiconductor device of claim 1 , wherein sidewalls of the first semiconductor device are free from an encapsulant.
6. The semiconductor device of claim 1 , further comprising an underfill material in physical contact with the first semiconductor device.
7. The semiconductor device of claim 1 , further comprising a second redistribution layer on an opposite side of the first semiconductor device than the first redistribution layer.
8. The semiconductor device of claim 7 , further comprising external connectors in contact with the second redistribution layer.
9. The semiconductor device of claim 7 , wherein the first semiconductor device comprises a through silicon via extending between the first redistribution layer and the second redistribution layer.
10. The semiconductor device of claim 9 , wherein the second semiconductor device comprises a passivation layer that is planar with the encapsulant.
11. The semiconductor device of claim 1 , further comprising a second encapsulant encapsulating the second semiconductor device.
12. A semiconductor device comprising:
an encapsulant with a first side and a second side opposite the first side;
a through via extending from the first side to the second side;
a first voltage regulator die extending from the first side to the second side;
a first redistribution layer electrically connected to the through via and the first voltage regulator die;
a first logic die electrically connected to the first voltage regulator die through the first redistribution layer; and
a heat spreader thermally connected to the first logic die.
13. The semiconductor device of claim 12 , further comprising a second voltage regulator extending from the first side to the second side.
14. The semiconductor device of claim 13 , further comprising a second logic die electrically connected to the first redistribution layer.
15. The semiconductor device of claim 14 , further comprising an I/O die electrically connected to the through via.
16. The semiconductor device of claim 12 , further comprising a second redistribution layer located on an opposite side of the first voltage regulator die than the first logic die.
17. The semiconductor device of claim 16 , further comprising a through silicon via extending through the first voltage regulator die and electrically connected to the second redistribution layer.
18. A method of manufacturing a semiconductor device, the method comprising:
encapsulating a via and a first voltage regulator die with a first encapsulant, wherein the first encapsulant is in a physical contact with the via;
forming a first redistribution layer on a first side of the first encapsulant, the first redistrbution layer in electrical connection with the via;
bonding a first logic die to the first redistribution layer, the first logic die in electrical connection with the first voltage regulator die;
bonding a second logic die to the first redistribution layer; and
encapsulating the first logic die and the second logic die with a second encapsulant, wherein the encapsulant the via and the first voltage regulator die further comprises encapsulating a second voltage regulator with the first encapsulant.
19. The method of claim 18 , further comprising forming a second redistribution layer on an opposite side of the first encapsulant from the first redistribution layer.
20. The method of claim 19 , wherein the forming the second redistribution layer electrically connects the second redistribution layer with through vias that extend through the first voltage regulator die.
21. The method of claim 18 , further comprising direct bonding an external connection with the via on an opposite side of the first encapsulant from the first redistribution layer.
22. A method of manufacturing a semiconductor device, the method comprising
forming a first redistribution layer over a first semiconductor die, wherein the first semiconductor die is a logic die;
forming vias on an opposite side of the first redistribution layer than the first semiconductor die;
placing a first integrated voltage regulator adjacent to the vias, wherein the first integrated voltage regulator comprises through silicon vias; and
encapsulating the first integrated voltage regulator and the vias.
23. The method of claim 22 , further comprising encapsulating the first semiconductor die and a second semiconductor die prior to the forming the first redistribution layer.
24. The method of claim 22 , further comprising forming a second redistribution layer on an opposite side of the first integrated voltage regulator than the first redistribution layer.
25. The method of claim 22 , wherein the first integrated voltage regulator comprises through silicon vias.