Multi-core processor based key protection method and system

1. A multi-core processor based key protection method, comprising:

setting up an Operating System (OS) supporting Symmetric Multi-Processing (SMP) on a multi-core processor, which comprises multiple cores;

configuring one of the multiple cores of the multi-core processor as a cryptographic operation core, wherein the cryptographic operation core exclusively occupies a cache and is prohibited from running other processes of the OS and dedicated to perform a public-key cryptographic operation;

performing the public-key cryptographic operation with the cryptographic operation core; and

storing a private key and an intermediate variable generated in a process of the public-key cryptographic operation in a cache exclusively occupied by the cryptographic operation core; wherein the private key is able to be obtained from the intermediate variable;

wherein storing the private key in the cache exclusively occupied by the cryptographic operation core includes:

storing the private key of a public-key cryptographic algorithm in a hard disk;

reading, by the cryptographic operation core, the private key stored in the hard disk; and

storing the private key read from the hard disk in the cache exclusively occupied by the cryptographic operation core.

2. The method according to claim 1 , wherein the private key stored in the hard disk is protected by a password; the method further comprises:

providing an interface for a user to input the password; and

decrypting, by the cryptographic operation core, the private key stored in the hard disk and protected by the password, which is input by the user, to obtain a plaintext of the private key;

wherein storing the private key in the cache exclusively occupied by the cryptographic operation core comprises: storing the plaintext of the private key in the cache exclusively occupied by the cryptographic operation core.

3. The method according to claim 2 , wherein the public-key cryptographic algorithm comprises: a public-key operation and a private-key operation, the private-key operation comprises: a digital signature and/or decryption operation; the method further comprises:

performing the digital signature and/or decryption operation with the private key and storing the intermediate variable and a result generated by the process of the public-key cryptographic operation in the cache exclusively occupied by the cryptographic operation core; and

synchronizing the result to a computer memory chip and performing a data cleanup operation for the cache exclusively occupied by the cryptographic operation core.

4. The method according to claim 3 , wherein storing the intermediate variable generated by the public-key cryptographic operation in the cache exclusively occupied by the cryptographic operation core comprises:

pointing a stack pointer register and a base pointer register of the cryptographic operation core to a static buffer with continuous addresses within the cache exclusively occupied by the cryptographic operation core before the digital signature and/or decryption operation is performed with the private key; and

storing the intermediate variable and the result generated by the process of the public-key cryptographic operation in the static buffer with the continuous addresses within the cache.

5. The method according to claim 4 , wherein before the stack pointer register and base pointer register of the cryptographic operation core point to the static buffer with the continuous addresses within the cache exclusively occupied by the cryptographic operation core, the method further comprises:

disabling a maskable interrupt of the cryptographic operation core and prohibiting the OS from occupying the cryptographic operation core;

placing the static buffer with the continuous addresses into the cache exclusively occupied by the cryptographic operation core; and

prohibiting replacing contents in caches except for the cache exclusively occupied by the cryptographic operation core.

6. The method according to claim 5 , wherein when the result is synchronized to the computer memory chip and the data cleanup operation is performed for the cache exclusively occupied by the cryptographic operation core, the method further comprises:

clearing a general purpose register; and

restoring all cores except for the cryptographic operation core to a normal cache access mode after the data cleanup operation is performed for the cache exclusively occupied by the cryptographic operation core.

7. A multi-core processor based key protection system, comprising:

a first module configured, to set up an Operating System (OS) supporting Symmetric Multi-Processing (SMP) on a multi-core processor, which comprises multiple cores, configure one of multiple cores of the multi-core processor as a cryptographic operation core, the one core exclusively occupies a cache and is configured to be prohibited from running other processes of the OS and dedicated to perform a public-key cryptographic operation; and

a second module configured, to perform the public-key cryptographic operation with the cryptographic operation core and store a private key and an intermediate variable generated in a process of the public-key cryptographic operation in a cache exclusively occupied by the cryptographic operation core, wherein the private key is able to be obtained from the intermediate variable;

wherein the second module comprises:

a first sub-module configured, to store the private key of a public-key cryptographic algorithm in a hard disk,

a second sub-module configured, to control the cryptographic operation core to read the private key stored in the hard disk; and

a third sub-module configured, to control the cryptographic operation core to store the private key read from the hard disk in the cache exclusively occupied by the cryptographic operation core.

8. The system according to claim 7 , wherein the private key stored in the hard disk is protected by a password,

the second sub-module is further configured, to control the cryptographic operation core to provide an interface for a user to input the password; and

a the third sub-module is further configured, to control the cryptographic operation core to decrypt the private key stored in the hard disk and protected by the password, which is input by the user, to obtain a plaintext of the private key and store the plaintext of the private key in the cache exclusively occupied by the cryptographic operation core.

9. The system according to claim 8 , wherein

the third sub-module is further configured to perform a digital signature and/or decryption operation with the private key and store the intermediate variable and a result generated by the process of the public-key cryptographic operation in the cache exclusively occupied by the cryptographic operation core and synchronize the result to a computer memory chip and perform a data cleanup operation for the cache exclusively occupied by the cryptographic operation core.

10. The system according to claim 9 , wherein the third sub-module is further configured to point a stack pointer register and a base pointer register of the cryptographic operation core to a static buffer with continuous addresses within the cache exclusively occupied by the cryptographic operation core before the digital signature and/or decryption operation is performed with the private key and store the intermediate variable and the result generated by the process of the public-key cryptographic operation in the static buffer with the continuous addresses within the cache.

11. The system according to claim 10 , wherein the third sub-module is further configured to disable a maskable interrupt of the cryptographic operation core, prohibit the OS from occupying the cryptographic operation core, place the static buffer with the continuous addresses into the cache exclusively occupied by the cryptographic operation core and prohibit replacing contents in caches except for the cache exclusively occupied by the cryptographic operation core before the stack pointer register and base pointer register of the cryptographic operation core point to the static buffer with the continuous addresses within the cache exclusively occupied by the cryptographic operation core.

12. The system according to claim 11 , wherein the third sub-module is further configured to synchronize the result to the computer memory chip, clear a general purpose register when the data cleanup operation is performed for the cache exclusively occupied by the cryptographic operation core and restore all cores except for the cryptographic operation core to a normal cache access mode.