Semiconductor devices and methods of fabricating the same

1. A semiconductor device comprising:

gate electrodes on a substrate, a longitudinal direction of each of the gate electrodes extending in a first direction and ones of the gate electrodes being arranged in the first direction;

first and second gate spacers extending in the first direction and on respective sidewalls of the ones of the gate electrodes, the first and second gate spacers being spaced apart from each other in a second direction that is different from the first direction; and

gate separation patterns, ones of the gate separation patterns being between two among the ones of the gate electrodes adjacent to each other in the first direction and between the first and second gate spacers,

wherein each of the gate electrodes has first opposing sidewalls that are spaced apart from each other in the first direction and second opposing sidewalls that are spaced apart from each other in the second direction,

wherein one of the first opposing sidewalls forms a first angle with a top surface of the substrate,

wherein one of the second opposing sidewalls forms a second angle with the top surface of the substrate, and

wherein the second angle is greater than the first angle.

2. The semiconductor device of claim 1 , wherein widths of the gate separation patterns are substantially equal to widths of the gate electrodes.

3. The semiconductor device of claim 1 , wherein the ones of the gate separation patterns are in contact with the first and second gate spacers.

4. The semiconductor device of claim 1 , wherein top surfaces of the gate separation patterns are substantially coplanar with top surfaces of the gate electrodes.

5. The semiconductor device of claim 1 , wherein bottom surfaces of the gate separation patterns are lower than bottom surfaces of the gate electrodes.

6. The semiconductor device of claim 1 , wherein the first and second gate spacers include an insulating material different from the gate separation patterns.

7. The semiconductor device of claim 1 , further comprising a device isolation layer defining active patterns on the substrate,

wherein each of the gate electrodes intersects one of the active patterns, and

wherein the gate separation patterns are disposed on the device isolation layer.

8. The semiconductor device of claim 1 , further comprising:

a gate insulating layer disposed between one of the gate electrodes and the substrate,

wherein the gate insulating layer extends between the one of the gate electrodes and the first and second gate spacers and between the one of the gate electrodes and one of the gate separation patterns.

9. The semiconductor device of claim 1 , wherein each of the gate separation patterns comprises a lower portion and an upper portion protruding from the lower portion,

wherein a width of the upper portion is smaller than a width of the lower portion, and

wherein the first and second gate spacers are disposed on the lower portion of one of the gate separation patterns.

10. The semiconductor device of claim 1 , wherein the gate electrodes comprise:

first gate electrodes arranged in the first direction and spaced apart from each other by a first distance in the first direction; and

second gate electrodes arranged in the first direction and spaced apart from each other by a second distance greater than the first distance in the first direction,

wherein the gate separation patterns comprise:

a first gate separation pattern on the first opposing sidewalls of two of the first gate electrodes, the first opposing sidewalls of the two of the first gate electrodes being spaced apart from each other in the first direction; and

a second gate separation pattern on the first opposing sidewalls of two of the second gate electrodes, the first opposing sidewalls of the two of the second gate electrodes being spaced apart from each other in the first direction.

11. The semiconductor device of claim 10 , wherein the second gate separation pattern comprises a first insulating pattern and a second insulating pattern that are formed of materials different from each other, and

wherein the first insulating pattern extends between the substrate and the second insulating pattern and between the second insulating pattern and the two of the second gate electrodes.

12. A semiconductor device comprising:

active patterns on a substrate; and

gate structures disposed on the substrate, each of the gate structures intersecting one of the active patterns,

wherein each of the gate structures comprises:

a pair of gate spacers extending in a first direction, the pair of gate spacers being spaced apart from each other in a second direction that is different from the first direction and defining a recess therebetween, and the recess extending longitudinally in the first direction in a plan view;

gate electrodes disposed between the pair of gate spacers, the gate electrodes being spaced apart from each other in the first direction, the gate electrodes extending longitudinally in the first direction in the plan view; and

gate separation patterns each disposed between the pair of gate spacers and between two of the gate electrodes adjacent to each other in the first direction,

wherein the gate electrodes and the gate separation patterns are in the recess.

13. The semiconductor device of claim 12 , further comprising a device isolation layer defining the active patterns,

wherein the gate separation patterns are disposed on the device isolation layer.

14. The semiconductor device of claim 13 , wherein a top surface of the device isolation layer is lower than top surfaces of the active patterns, and

wherein one of the gate electrodes covers the top surface and a sidewall of one of the active patterns.

15. The semiconductor device of claim 12 , wherein each of the gate electrodes has first opposing sidewalls that are spaced apart from each other in the first direction, and second opposing sidewalls that are spaced apart from each other in the second direction,

wherein one of the first opposing sidewalls forms a first angle with a top surface of the substrate,

wherein one of the second opposing sidewalls forms a second angle with the top surface of the substrate, and

wherein the second angle is greater than the first angle.

16. The semiconductor device of claim 12 , wherein the pair of gate spacers includes an insulating material different from the gate separation patterns.

17. The semiconductor device of claim 12 , wherein top surfaces of the gate separation patterns are substantially coplanar with top surfaces of the gate electrodes.

18. The semiconductor device of claim 12 , wherein bottom surfaces of the gate separation patterns are lower than bottom surfaces of the gate electrodes.

19. The semiconductor device of claim 12 ,

wherein the second direction is perpendicular to the first direction, and

wherein one of the gate electrodes is in a first portion of the recess, one of the gate separation patterns is disposed in a second portion of the recess, and the first portion and the second portion of the recess have an equal width in the second direction.

20. A semiconductor device comprising:

gate electrodes on a substrate, a longitudinal direction of each of the gate electrodes extending in a first direction and ones of the gate electrodes being arranged in the first direction;

first and second gate spacers extending in the first direction and on respective sidewalls of the ones of the gate electrodes, the first and second gate spacers being spaced apart from each other in a second direction that is different from the first direction; and

gate separation patterns, ones of the gate separation patterns being between two among the ones of the gate electrodes adjacent to each other in the first direction and between the first and second gate spacers,

wherein widths of the gate separation patterns are substantially equal to widths of the gate electrodes.