Methods of fabricating a semiconductor device

1. A method of fabricating a semiconductor device, comprising:

sequentially forming a lower mold layer and an intermediate mold layer on a substrate with a first region and a second region;

forming first upper mold patterns and first spacers on the intermediate mold layer, the first upper mold patterns and the first spacers being formed on the first and second regions, respectively, using different, but partially overlapping processes;

etching the intermediate mold layer using the first upper mold patterns and the first spacers as an etch mask to form first and second intermediate mold patterns, respectively;

forming second spacers on sidewalls of the first and second intermediate mold patterns;

etching the lower mold layer using the second spacers as an etch mask to form lower mold patterns; and

etching an upper portion of the substrate using the lower mold patterns as an etch mask to form active patterns.

2. The method of claim 1 , wherein the first upper mold patterns have a width that is different from a maximum width of the first spacers.

3. The method of claim 2 , wherein the forming of the first upper mold patterns and the first spacers comprises:

forming first and second upper mold patterns on the intermediate mold layer to be disposed on the first and second regions, respectively;

forming an etching-prevention pattern on at least one of the first upper mold patterns;

forming the first spacers on sidewalls of the etching-prevention pattern and sidewalls of the second upper mold patterns; and

removing the etching-prevention pattern and the second upper mold patterns,

wherein the at least one of the first upper mold patterns remains after the removing of the etching-prevention pattern and the second upper mold patterns.

4. The method of claim 3 ,

wherein the etching-prevention pattern is formed of a material having an etch selectivity with respect to the second upper mold patterns,

wherein the forming of the first spacers comprises:

forming a first spacer layer on the etching-prevention pattern and the second upper mold patterns; and

anisotropically etching the first spacer layer to expose a top surface of the etching-prevention pattern and top surfaces of the second upper mold patterns, and

wherein the removing of the etching-prevention pattern and the second upper mold patterns comprises:

selectively removing the second upper mold patterns with the exposed top surfaces, while using the etching-prevention pattern to prevent the first upper mold patterns from being etched; and

selectively removing the etching-prevention pattern, after the removing of the second upper mold patterns.

5. The method of claim 3 ,

wherein the forming of the second intermediate mold patterns comprises etching the intermediate mold layer using the first spacers positioned on both sidewalls of the etching-prevention pattern as an etch mask to form second intermediate mold patterns on the first region,

wherein some of the second spacers are on sidewalls of the second intermediate mold patterns positioned on the first region, and

wherein the active patterns comprises dummy active patterns formed using the second spacers on sidewalls of the second intermediate mold patterns positioned on the first region.

6. The method of claim 2 ,

wherein the forming of the lower mold patterns comprises:

removing the first and second intermediate mold patterns;

etching the lower mold layer using the second spacers on the first region as an etch mask to form first lower mold patterns; and

etching the lower mold layer using the second spacers on the second region as an etch mask to form second lower mold patterns,

wherein the forming of the active patterns comprises etching the upper portion of the substrate using the first and second lower mold patterns as an etch mask to form first and second active patterns, respectively,

wherein the first and second lower mold patterns are formed at the same time, and

wherein the first and second active patterns are formed at the same time.

7. The method of claim 2 , wherein the width of each of the first upper mold patterns is substantially equal to a distance between a pair of the active patterns on the first region.

8. The method of claim 2 , wherein each of the first spacers has the maximum width that is substantially equal to a distance between a pair of the active patterns on the second region.

9. The method of claim 2 , wherein ones of the first upper mold patterns have the width that is larger than the maximum width of ones of the first spacers.

10. The method of claim 2 , wherein the substrate further comprises a third region, and

wherein the method further comprises:

forming a third upper mold pattern on the intermediate mold layer and on the third region, the third upper mold pattern being formed at the same time as the first upper mold patterns;

etching the intermediate mold layer using the third upper mold pattern as an etch mask to form a third intermediate mold pattern;

etching the lower mold layer using the third intermediate mold pattern as an etch mask to form a third lower mold pattern; and

etching the upper portion of the substrate using the third lower mold pattern as an etch mask to form a key pattern.

11. The method of claim 10 ,

wherein the second spacers are formed on sidewalls of the third intermediate mold pattern, and

wherein the forming of the third lower mold pattern comprises etching the lower mold layer using the third intermediate mold pattern and the second spacers as an etch mask.

12. The method of claim 2 , further comprising:

forming device isolation layers to fill trenches between the active patterns; and

forming gate electrodes to cross the active patterns.

13. The method of claim 12 ,

wherein the trenches comprise a first trench between a pair of the active patterns on the first region and a second trench between a pair of the active patterns on the second region, and

wherein the first trench is formed to have a width larger than that of the second trench.

14. A method of fabricating a semiconductor device, comprising:

sequentially forming a lower mold layer and an intermediate mold layer on a substrate with a first region and a second region;

forming first and second upper mold patterns on the intermediate mold layer disposed on the first and second regions, respectively;

forming an etching-prevention pattern on at least one of the first upper mold patterns;

forming first spacers on sidewalls of the second upper mold patterns;

removing the etching-prevention pattern and the second upper mold patterns;

etching the intermediate mold layer using the first upper mold patterns and the first spacers as an etch mask to form first and second intermediate mold patterns, respectively;

forming second spacers on sidewalls of the first and second intermediate mold patterns;

etching the lower mold layer using the second spacers as an etch mask to form lower mold patterns; and

etching an upper portion of the substrate using the lower mold patterns as an etch mask to form active patterns.

15. The method of claim 14 ,

wherein the etching-prevention pattern is formed of a material having an etch selectivity with respect to the second upper mold patterns,

wherein forming the first spacers comprises:

forming a first spacer layer on the second upper mold patterns; and

anisotropically etching the first spacer layer to expose top surfaces of the second upper mold patterns, and

wherein removing the etching-prevention pattern and the second upper mold patterns comprises:

selectively removing the second upper mold patterns with the exposed top surfaces, while using the etching-prevention pattern to prevent the first upper mold patterns from being etched; and

selectively removing the etching-prevention pattern after removing the second upper mold patterns.

16. The method of claim 14 , wherein the first upper mold patterns have a width that is larger than a maximum width of the first spacers.

17. A method of fabricating a semiconductor device, comprising:

sequentially forming a lower mold layer and an intermediate mold layer on a substrate with a first region and a second region;

forming a first upper mold pattern on the intermediate mold layer of the first region and a first spacer on the intermediate mold layer of the second region;

etching the intermediate mold layer using the first upper mold pattern and the first spacer as an etch mask to form a first intermediate mold pattern and a second intermediate mold pattern, respectively;

forming second spacers on sidewalls of the first and second intermediate mold patterns;

etching the lower mold layer using the second spacers as an etch mask to form lower mold patterns; and

etching an upper portion of the substrate using the lower mold patterns as an etch mask to form active patterns,

wherein the first upper mold pattern has a width that is different from a maximum width of the first spacer.

18. The method of claim 17 , wherein the width of the first upper mold pattern is substantially equal to a distance between a pair of the active patterns on the first region.

19. The method of claim 17 , wherein the maximum width of the first spacer is substantially equal to a distance between a pair of the active patterns on the second region.

20. The method of claim 17 , wherein the width of the first upper mold pattern is larger than the maximum width of the first spacer.