IP Library › Granted Patent US 9,922,928
Granted Patent B2
US 9,922,928 · App. 15/217,983 · Granted Mar 20, 2018

Semiconductor device and method of manufacturing semiconductor device

Inventor: Takashi Tonegawa (Ibaraki, JP)
Assignee: RENESAS ELECTRONICS CORPORATION
H01L23/5283H01L21/31H01L21/311H01L21/31056H01L21/44H01L23/528H01L23/53295H01L24/03H01L24/08H01L24/48H01L24/85H01L23/3171H01L23/481H01L23/4827H01L23/522H01L23/53223H01L24/29H01L24/32H01L24/37H01L24/45H01L24/73H01L24/84H01L2224/0215H01L2224/02126H01L2224/02145H01L2224/02206H01L2224/02215H01L2224/031H01L2224/0345H01L2224/03464H01L2224/03522H01L2224/04034H01L2224/04042H01L2224/05007H01L2224/05017H01L2224/05023H01L2224/05025H01L2224/05027H01L2224/05083H01L2224/05124H01L2224/05155H01L2224/05164H01L2224/05558H01L2224/05562H01L2224/05568H01L2224/05582H01L2224/05644H01L2224/05655H01L2224/05664H01L2224/29339H01L2224/32245H01L2224/37147H01L2224/45147H01L2224/48247H01L2224/48463H01L2224/48799H01L2224/48844H01L2224/73265H01L2224/8385H01L2224/84801H01L2224/85045H01L2224/85181H01L2224/85203H01L2924/0509H01L2924/05042H01L2924/05442H01L2924/07025H01L2924/1203H01L2924/1206H01L2924/13055H01L2924/13091H01L2924/15747H01L2924/35121
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Quick Facts
Patent No.
US 9,922,928
App. No.
15/217,983
Granted
Mar 20, 2018
Kind
B2
Abstract

Properties of a semiconductor device are improved. A semiconductor device is configured so as to have a protective film provided over an interconnection and having an opening, and a plating film provided in the opening. A slit is provided in a side face of the opening, and the plating film is also disposed in the slit. Thus, the slit is provided in the side face of the opening, and the plating film is also grown in the slit. This results in a long penetration path of a plating solution during subsequent formation of the plating film. Hence, a corroded portion is less likely to be formed in the interconnection (pad region). Even if the corroded portion is formed, a portion of the slit is corroded prior to the interconnection (pad region) at a sacrifice, making it possible to suppress expansion of the corroded portion into the interconnection (pad region).

Claims (52)

1. A semiconductor device, comprising:

a first insulating film provided above a semiconductor substrate;

a first interconnection provided over the first insulating film;

a second insulating film provided over the first interconnection and having a first opening;

a plating film provided in the first opening; and

a slit penetrating a side face of the second insulating film adjacent to the first opening,

wherein a bottom of the first opening is a pad region being part of the first interconnection,

wherein the plating film is also provided in the slit,

wherein the first interconnection contains aluminum (Al), and

wherein the plating film contains a metal selected from nickel (Ni), gold (Au), and palladium (Pd).

2. The semiconductor device according to claim 1 ,

wherein the plating film contains nickel (Ni), and

further comprising a second plating film provided on the plating film and containing gold (Au).

3. The semiconductor device according to claim 2 , further comprising a third plating film containing palladium (Pd) between the plating film and the second plating film.

4. The semiconductor device according to claim 1 , further comprising one of a bonding wire and a metal frame provided over the plating film.

5. The semiconductor device according to claim 1 , further comprising a third insulating film that is provided over the second insulating film and has a second opening over the first opening.

6. The semiconductor device according to claim 5 , wherein the second insulating film is a film selected from a silicon nitride film, a silicon oxynitride film, and a silicon oxide film.

7. The semiconductor device according to claim 6 , wherein the third insulating film is a polyimide film.

8. The semiconductor device according to claim 1 , wherein the plating film fills the first opening and the slit.

9. The semiconductor device according to claim 1 ,

wherein a first portion of the plating film is formed over a first portion of the second insulating film,

wherein a second portion of the plating film is formed within the slit, and

wherein the first portion of the second insulating film is between the first and second portions of the plating film.

10. A method of manufacturing a semiconductor device, the method comprising:

(a) forming a first insulating film above a semiconductor substrate;

(b) forming a first interconnection over the first insulating film;

(c) forming a second insulating film over the first interconnection;

(d) removing the second insulating film over the first interconnection, thereby forming a first opening exposing a pad region that is part of the first interconnection; and

(e) after (d), forming a plating film over the pad region,

wherein in (d), a slit is formed so as to penetrate a side face of the second insulating film adjacent to the first opening,

wherein in (e), the plating film is formed in the slit,

wherein the first interconnection contains aluminum (Al), and

wherein the plating film contains a metal selected from nickel (Ni), gold (Au), and palladium (Pd).

11. The method according to claim 10 , wherein (d) comprises removing the second insulating film by dry etching.

12. The method according to claim 11 , wherein the dry etching in (d) involves overetching performed after the pad region is exposed.

13. The method according to claim 10 ,

wherein (e) comprises:

forming the plating film containing nickel (Ni) over the pad region, and

forming a second plating film containing gold (Au) over the plating film.

14. The method according to claim 10 ,

wherein (e) comprises:

forming the plating film containing nickel (Ni) over the pad region,

forming a second plating film containing palladium (Pd) over the plating film, and

forming a third plating film containing gold (Au) over the second plating film.

15. The method according to claim 10 , further comprising:

(f) providing one of a bonding wire and a metal frame over the plating film.

16. The method according to claim 10 , further comprising:

between (d) and (e),

(g) forming a third insulating film over the second insulating film; and

(h) forming a second opening in the third insulating film,

wherein the second opening in (h) is formed over the first opening.

17. The method according to claim 16 , wherein the second insulating film is a film selected from a silicon nitride film, a silicon oxynitride film, and a silicon oxide film, and the third insulating film is a polyimide film.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 23, 2016
From: TONEGAWA, TAKASHI
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 039238/0465 →
Priority Claims (1)
JP 2015-193172 · Sep 30, 2015 · national
Continuity (1)
Related Publication 20170092605A1 · Mar 30, 2017