IP Library Granted Patent US 9,923,049
Granted Patent B2
US 9,923,049 · App. 14/988,894 · Granted Mar 20, 2018

Compound semiconductor device and method for manufacturing the same

Inventor: Naoya Okamoto (Isehara, JP)
Assignee: FUJITSU LIMITED
H01L29/045H01L21/02609H01L21/8252H01L27/0605H01L27/0629H01L29/0649H01L29/205H01L29/66219H01L29/7786H01L29/882H01L21/0254H01L21/02458H01L23/3171H01L27/0623H01L29/155H01L29/2003H01L29/432H01L2924/0002
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Quick Facts
Patent No.
US 9,923,049
App. No.
14/988,894
Granted
Mar 20, 2018
Kind
B2
Abstract

A compound semiconductor device includes: a substrate; a first barrier layer of a nitride semiconductor formed over the substrate; a well layer of a nitride semiconductor formed over the first barrier layer; and a second barrier layer of a nitride semiconductor formed over the well layer, wherein the first barrier layer, the well layer, and the second barrier layer each include a first region having, as an upper surface, a (0001) plane in terms of crystal orientation and a second region having, as an upper surface, a (000-1) plane in terms of crystal orientation, the first region of the first barrier layer, the first region of the well layer, and the first region of the second barrier layer are stacked, the second region of the first barrier layer, the second region of the well layer, and the second region of the second barrier layer are stacked.

Claims (31)

1. A compound semiconductor device comprising:

a substrate;

a nitride semiconductor layer formed over the substrate;

a first barrier layer of a nitride semiconductor formed over the substrate a part of a first region of the nitride semiconductor layer;

a first collector electrode formed over another part of the first region of the nitride semiconductor layer;

a first well layer of a nitride semiconductor formed over the first barrier layer;

a second barrier layer of a nitride semiconductor formed over the first well layer;

a first emitter electrode formed over the second barrier layer;

a third barrier layer of a nitride semiconductor formed over a part of a second region of the nitride semiconductor layer, the second region is adjacent to the first region;

a second collector electrode formed over another part of the second region of the nitride semiconductor layer;

a second well layer of a nitride semiconductor formed over the third barrier layer;

a fourth barrier layer of a nitride semiconductor formed over the second well layer; and

a second emitter electrode formed over the fourth barrier layer, wherein

an upper surface of the first region of the nitride semiconductor layer, an upper surface of the first barrier layer, an upper surface of the first well layer, and an upper surface of the second barrier layer have a (0001) plane in terms of crystal orientation,

an upper surface of the second region of the nitride semiconductor layer, an upper surface of the third barrier layer, an upper surface of the second well layer, and an upper surface of the fourth barrier layer have a (000-1) plane in terms of crystal orientation,

the first emitter electrode and the second emitter electrode are electrically coupled to each other, and

the first collector electrode and the second collector electrode are electrically coupled to each other.

2. The compound semiconductor device according to claim 1 ,

wherein the first barrier layer, the second barrier layer, the third barrier layer and the second barrier layer each include an In x Al y Ga 1-x-y N (0≤x<1, 0≤y<1, 0<x+y<1) layer, and

the first well layer and second well layer each includes an In z Ga 1-z N (0≤z<1) layer.

3. The compound semiconductor device according to claim 1 ,

wherein an ion-implanted region is formed at a boundary between the first and the third barrier layers, between the first and the second well layers, and between the second and the fourth barrier layers.

4. The compound semiconductor device according to claim 1 ,

wherein a passivation film is formed at a boundary between the first and the third barrier layers, between the first and the second well layers, and between the second and the fourth barrier layers.

5. The compound semiconductor device according to claim 1 ,

wherein the substrate is a sapphire substrate, a silicon carbide substrate, a gallium nitride substrate, or an aluminum nitride substrate.

6. The compound semiconductor device according to claim 1 ,

wherein the first emitter electrode and the second emitter electrode are integrated with each other, and

the first collector electrode and the second collector electrode are integrated with each other.

7. The compound semiconductor device according to claim 1 , further comprising:

a high-electron mobility transistor formed on the substrate.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 13, 2016
From: OKAMOTO, NAOYA
To: FUJITSU LIMITED
Reel/Frame 037471/0562 →
Priority Claims (1)
JP 2015-010723 · Jan 22, 2015 · national
Continuity (1)
Related Publication 20160218201A1 · Jul 28, 2016