Runtime verification

1. A system, comprising:

a hardware processor;

a shared memory storing embedded controller instructions; and

an I/O controller located between the shared memory and the hardware processor and wherein the I/O controller is located between the shared memory and an embedded controller, the embedded controller to:

verify integrity of the embedded controller instructions stored in the shared memory during runtime of the hardware processor, wherein the embedded controller instructions are executable in the embedded controller, and wherein the shared memory is accessible, via the I/O controller, by the embedded controller and the processor during runtime of the hardware processor, wherein verifying the integrity of the embedded controller instructions stored in the shared memory during runtime of the hardware processor that provides comparatively earlier identification of compromised embedded controller instructions as compared to approaches that occur prior to the runtime of the hardware processor, approaches that occur during low power states of the hardware processor, or a combination of both; and

cause repair of the compromised embedded controller instructions.

2. The system of claim 1 , I/O controller is to facilitate the shared memory to receive runtime access requests from the embedded controller and runtime access requests from the hardware processor.

3. The system of claim 2 , wherein the runtime access requests from the embedded controller are provided via an enhanced serial peripheral interface bus to the I/O controller during runtime of the hardware processor.

4. The system of claim 2 , wherein the runtime access requests from the embedded controller and the runtime access requests from the hardware processor are transmitted by the I/O controller via a shared bus to the shared memory.

5. The system of claim 2 , wherein runtime comprises execution of the I/O controller in an advanced configuration and power (ACPI) S0 state.

6. The system of claim 1 , wherein the embedded controller causes the embedded controller instructions to be repaired during runtime.

7. The system of claim 1 , wherein the embedded controller verifies the embedded controller instructions stored in the shared memory periodically during runtime of the hardware processor.

8. The system of claim 1 , wherein the embedded controller is further to verify the embedded controller instructions are from a trusted source.

9. A non-transitory machine-readable medium including instructions executable to:

transmit, via an enhanced serial peripheral bus and an I/O controller, communications between an embedded controller and a shared memory during runtime, wherein the shared memory is accessible by the embedded controller and hardware processor during runtime, wherein the I/O controller is located between the shared memory and an embedded controller;

verify, during runtime of the hardware processor, integrity of embedded controller instructions, system instructions, or data stored in the shared memory, wherein the instructions to verify the embedded controller instructions, the system instructions, or the data stored in the shared memory provide comparatively earlier identification of compromised embedded controller instructions, system instructions, or data as compared to approaches that occur prior to the runtime of the hardware processor, approaches that occur during low power states of the hardware processor, or a combination of both; and

repair the compromised embedded controller instructions, system instructions, or data.

10. The medium of claim 9 , further comprising instructions to add a result of the verification to an event log.

11. The medium of claim 9 , further comprising instructions to send a notification to have the CPU enter a low power state when the embedded controller instructions, system instructions, or data are compromised.

12. A method, comprising:

transmitting, via an enhanced serial peripheral bus and an I/O controller, communications between a controller and a shared memory during runtime of a hardware processor, wherein the shared memory is accessible by the embedded controller and the hardware processor during runtime, wherein the I/O controller is located between the shared memory and an embedded controller;

verifying, during runtime of a hardware processor, integrity of embedded controller instructions, system instructions, or data stored in the shared memory, wherein the verifying includes detection of compromised embedded controller instructions, system instructions, or data, wherein the verifying of the embedded controller instructions, the system instructions, or the data provides comparatively earlier identification of compromised embedded controller instructions, system instructions, or data as compared to approaches that occur prior to the runtime of the hardware processor, approaches that occur during low power states of the hardware processor, or a combination of both; and

repairing the compromised embedded controller instructions, system instructions, or data.

13. The method of claim 12 , wherein repairing comprises repairing the compromised embedded controller instructions, system instructions, or data during runtime of the hardware processor.

14. The method of claim 13 , wherein verifying the embedded controller instructions in the shared memory comprises verifying the embedded controller instructions are part of basic input/output system (BIOS) instructions stored in the shared memory.

15. The method of claim 13 , comprising recording result of verification in a private non-volatile memory.

16. The medium of claim 9 , further comprising instructions to cryptographically validate that the embedded controller instructions, system instructions, or data are from a trusted source.

17. The method of claim 12 , wherein verifying further comprises cryptographically validating that the embedded controller instructions, system instructions, or data are from a trusted source.