Wordline adjustment scheme
A memory and a method for operating a memory are provided. The memory includes a memory cell having a transistor and a wordline driver outputting a wordline coupled to the memory cell. The wordline driver adjusts a voltage level of the wordline to compensate for a parameter of the transistor. The method includes asserting a wordline voltage to access a memory cell having a transistor and adjusting the wordline voltage to compensate for a parameter of the transistor. Another memory is provided. The memory includes a memory cell and a wordline driver outputting a wordline coupled to the memory cell. The wordline driver adjusts a voltage level of the wordline based on a feedback of the wordline.
1. A memory, comprising:
a memory cell comprising a transistor; and
a wordline driver coupled to the memory cell by a wordline, the wordline driver being configured to adjust a voltage level of the wordline,
wherein the wordline driver further comprises a pull-down transistor coupled to the wordline to adjust the voltage level and a passgate transistor to bias the pull-down transistor, the pull-down transistor separate from a buffer driving the wordline.
2. The memory of claim 1 , wherein the parameter comprises a speed of the transistor based on at least the transconductance of the transistor.
3. The memory of claim 2 , wherein the transistor is an n-type transistor, and the wordline driver is further configured to pull down a voltage level of the wordline more in a case of faster n-type transistor, and to pull down the voltage level of the wordline less in a case of slower n-type transistor.
4. The memory of claim 2 , wherein the parameter further comprises at least one of a threshold voltage of the transistor or a temperature of the transistor.
5. The memory of claim 1 , wherein the pull-down transistor is directly coupled to the wordline to adjust the voltage level.
6. The memory of claim 5 , wherein the passgate transistor is coupled between the wordline and a gate of the pull-down transistor.
7. The memory of claim 6 , wherein the pull-down transistor comprises a gate, and wherein the passgate transistor is coupled between the wordline and the gate.
8. The memory of claim 7 , wherein each of the pull-down transistor and passgate transistor comprises an n-channel transistor.
9. The memory of claim 1 , wherein the memory cell comprises a latch and a bitline, and wherein the transistor comprises an access transistor coupling the bitline to the latch.
10. The memory of claim 9 , wherein the latch comprises at least one p-type transistor and at least one n-type transistor, wherein the at least one p-type transistor and the at least one n-type transistor are of a same size.
11. The memory of claim 10 , wherein the at least one p-type transistor, the at least one n-type transistor, and the access transistor comprise finFET transistors and comprise a same number of fin or fins.
12. A method for operating a memory, comprising:
asserting a wordline voltage to access a memory cell comprising a transistor;
adjusting the wordline voltage;
pulling down the wordline voltage by a pull-down transistor, the pull-down transistor separate from a buffer driving the wordline; and
biasing the pull-down transistor by a passgate transistor.
13. The method of claim 12 , wherein the parameter comprises a speed of the transistor based on at least the transconductance of the transistor.
14. The method of claim 13 , wherein the transistor is an n-type transistor, further comprises
pulling down the wordline voltage more in a case of faster n-type transistor; and
pulling down the wordline voltage less in a case of slower n-type transistor.
15. The method of claim 13 , wherein the parameter further comprises at least one of a threshold voltage of the transistor or a temperature of the transistor.
16. The method of claim 12 , wherein pulling down the wordline voltage by a pull-down transistor comprises pulling down the wordline voltage by a pull-down transistor directly coupled to the wordline.
17. The method of claim 16 , wherein biasing the pull-down transistor by a passgate transistor comprises coupling the passgate transistor between the wordline and a gate of the pull-down transistor.
18. The method of claim 17 , further comprising
coupling, by the passgate transistor, a gate of the pull-down transistor and the wordline voltage.
19. The method of claim 18 , wherein each of the pull-down transistor and passgate transistor comprises an n-channel transistor.
20. The method of claim 12 , wherein the memory cell comprises a latch and a bitline, and wherein the transistor comprises an access transistor coupling the bitline to the latch.
21. The method of claim 20 , wherein the latch comprises at least one p-type transistor and at least one n-type transistor, wherein the at least one p-type transistor and the at least one n-type transistor are of a same size.
22. The method of claim 21 , wherein the at least one p-type transistor, the at least one n-type transistor, and the access transistor comprise finFET transistors and comprise a same number of fin or fins.
23. A memory, comprising:
a memory cell; and
a wordline driver coupled to the memory cell by a wordline, the wordline driver being configured to adjust a voltage level of the wordline based on a feedback of the wordline,
wherein the wordline driver further comprises a pull-down transistor coupled to the wordline to adjust the voltage level and a passgate transistor to bias the pull-down transistor, the pull-down transistor separate from a buffer driving the wordline.
24. The memory of claim 23 , wherein the pull-down transistor is configured to pull down a voltage level of the wordline, and wherein the pull-down transistor comprises a gate coupled to the wordline.
25. The memory of claim 24 , wherein the gate of the pull-down transistor is electrically connected to the wordline to control the pulling down of the voltage level of the wordline.
26. The memory of claim 24 , wherein the passgate transistor is coupled between the wordline and the gate.
27. The memory of claim 26 , wherein the memory cell comprises a latch having at least one p-type transistor and at least one n-type transistor, wherein the at least one p-type transistor and the at least one n-type transistor are of a same size.
28. The memory of claim 27 , wherein the memory cell further comprises an access transistor coupling the latch to a bitline, and wherein the at least one p-type transistor, the at least one n-type transistor, and the access transistor comprise finFET transistors and comprise a same number of fin or fins.
29. A memory, comprising:
a memory cell comprising a transistor; and
a wordline driver coupled to the memory cell by a wordline, the wordline driver being configured to adjust a voltage level of the wordline,
wherein the wordline driver further comprises a pull-down transistor coupled to the wordline to adjust the voltage level and a passgate transistor to bias the pull-down transistor, wherein adjusting the voltage level of the wordline comprises pulling down the wordline when the wordline driver outputs a logic 1.