IP Library Granted Patent US 9,929,039
Granted Patent B2
US 9,929,039 · App. 15/129,328 · Granted Mar 27, 2018

Method for manufacture of a semiconductor wafer suitable for the manufacture of an SOI substrate, and SOI substrate wafer thus obtained

Inventors: Didier Dutartre (Meylan, FR); Herve Jaouen (Saint Nazaire les Eymes, FR)
Assignee: STMicroelectronics SA
H01L21/7624H01L21/0245H01L21/02488H01L21/02502H01L21/02513H01L21/02532H01L21/02595
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Quick Facts
Patent No.
US 9,929,039
App. No.
15/129,328
Granted
Mar 27, 2018
Kind
B2
Abstract

A semiconductor wafer suitable for fabricating an SOI substrate is provided by: producing a first layer of polycrystalline semiconductor on a top side of a semiconductor carrier; then forming an interface zone on a top side of the first layer, wherein the interface zone has a structure different from a crystal structure of the first layer; and then producing a second layer of polycrystalline semiconductor on the interface zone.

Claims (36)

1. Process for producing a silicon-on-insulator substrate, including:

producing a carrier substrate, and

producing a semiconductor film located on top of a buried insulating layer itself located on top of the carrier substrate,

wherein producing the carrier substrate comprises producing, on one side of a semiconductor carrier, a stack located between said semiconductor carrier and said buried insulating layer and including at least one initial structure,

wherein producing said at least one initial structure of the stack comprises the following successive steps:

producing, on said one side of said semiconductor carrier, a first layer of polycrystalline semiconductor having a first thickness;

forming an interface zone on a top side of said first layer, said interface zone having a structure different from a crystal structure of said first layer; and

producing, on said interface zone, a second layer of polycrystalline semiconductor having a second thickness, wherein the second thickness is less than the first thickness.

2. Process according to claim 1 , wherein forming the interface zone comprises exposing the top side of the first layer to an oxidizing environment in order to oxidize said top side of the first layer.

3. Process according to claim 1 , wherein forming the interface zone comprises amorphizing the top side of said first layer.

4. Process according to claim 1 , wherein producing said stack further comprises producing at least one additional structure on said second layer by producing a new interface zone surmounted by a new layer of polycrystalline semiconductor, wherein layers of the stack of the plurality of layers of polycrystalline semiconductor are respectively separated by interface zones having a structure different from the crystal structure of said layers of polycrystalline semiconductor.

5. Process according to claim 4 , wherein a last layer of plurality of layer of polycrystalline semiconductor of said stack has a thickness smaller than 20% of a total thickness of preceding layers of polycrystalline semiconductor of said stack.

6. A process, comprising:

producing a first layer of polycrystalline semiconductor above a semiconductor carrier, said first layer having a divergent pseudo-columnar crystal arrangement with a grouping of grains having a first size; then

forming an interface zone on a top side of said first layer, said interface zone having a structure different from a crystal structure of said first layer; then

producing a second layer of polycrystalline semiconductor on said interface zone, said second layer having a divergent pseudo-columnar crystal arrangement with a grouping of grains having a second size smaller than the first size.

7. The process of claim 6 , wherein the first layer has a thickness between 500 nm and 5000 nm and the second layer has a thickness between 100 nm and 300 nm.

8. The process of claim 6 , wherein forming the interface zone comprises oxidizing the top size of said first layer.

9. The process of claim 6 , wherein forming the interface zone comprises amorphizing the top size of said first layer.

10. The process of claim 6 , further comprising:

forming a buried oxide layer above a top surface of the second layer of polycrystalline semiconductor; and

forming a semiconductor film on a top surface of the buried oxide layer to as to produce a semiconductor on insulator (SOI) substrate.

11. The process of claim 6 , wherein the first layer has a first thickness and the second layer has a second thickness that is less than the first thickness.

12. A process for producing a silicon-on-insulator substrate, including:

producing a carrier substrate, and

producing a semiconductor film located on top of a buried insulating layer itself located on top of the carrier substrate,

wherein producing the carrier substrate comprises producing, on one side of a semiconductor carrier, a stack located between said semiconductor carrier and said buried insulating layer, wherein producing said stack comprises the following successive steps:

producing a first layer of polycrystalline semiconductor in contact with a top side of said semiconductor carrier, said first layer having a first thickness and a corresponding first concentration of grain boundaries;

forming an interface zone in contact with a top side of said first layer, said interface zone having a structure different from a crystal structure of said first layer; and

producing a second layer of polycrystalline semiconductor in contact with a top side of the interface zone, said second layer having a second thickness and a corresponding second concentration of grain boundaries, wherein the second thickness is less than the first thickness and the second concentration is greater than the first concentration.

13. The process according to claim 12 , wherein the second thickness is no more than 20% of the first thickness.

14. The process according to claim 12 , wherein forming the interface zone comprises exposing the top side of the first layer to an oxidizing environment in order to form an interface zone comprising a semiconductor oxide layer.

15. The process according to claim 12 , wherein forming the interface zone comprises amorphizing the top side of said first layer in order to form an interface zone comprising an amorphous semiconductor layer.

16. The process according to claim 12 , wherein producing said stack further comprises producing a third layer of polycrystalline semiconductor above the second layer and separated from the second layer by a further interface zone.

17. The process according to claim 16 , wherein the third layer has a third thickness and a corresponding third concentration of grain boundaries, wherein the third thickness is less than both the first and second thicknesses and the third concentration is greater than both the first and second concentrations.

18. The process according to claim 17 , wherein the third thickness of the third layer is no more than 20% of a total thickness of preceding layers of said stack.

Assignments (2)
CHANGE OF NAME Recorded Feb 23, 2024
From: STMICROELECTRONICS SA
To: STMICROELECTRONICS FRANCE
Reel/Frame 066663/0136 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 28, 2016
From: DUTARTRE, DIDIER; JAOUEN, HERVE
To: STMICROELECTRONICS SA
Reel/Frame 039874/0037 →
Priority Claims (1)
FR 14 52845 · Mar 31, 2014 · national
Continuity (1)
Related Publication 20170103913A1 · Apr 13, 2017