Sample-and-hold circuit with RTS noise reduction by periodic mode switching
A sample-and-hold-circuit includes an amplifier transistor, a resistor connected between a source terminal of the amplifier and a voltage, a first switch connected in parallel with the resistor, and a second switch connected between a gate terminal of the amplifier transistor and the voltage. When the first switch is closed and the second switch is open, the amplifier transistor is in an inversion mode; and when the first switch is open and the second switch is closed, the amplifier transistor is in an accumulation mode.
1. A sample-and-hold circuit, comprising:
an amplifier transistor;
a resistor connected between a source terminal of the amplifier transistor and a predetermined voltage;
a first switch connected in parallel with the resistor; and
a second switch connected between a gate terminal of the amplifier transistor and the predetermined voltage.
2. The sample-and-hold circuit according to claim 1 , wherein
in a case where the first switch is closed and the second switch is open, the amplifier transistor is in an inversion mode, and
in a case where the first switch is open and the second switch is closed, the amplifier transistor is in an accumulation mode.
3. The sample-and-hold circuit according to claim 2 , wherein the first switch and the second switch are controlled such that when the first switch is open, the second switch is closed;
and when the first switch is closed, the second switch is opened.
4. The sample-and-hold circuit according to claim 2 , wherein the amplifier transistor is switched between the inversion mode and the accumulation mode in an alternating manner.
5. The sample-and-hold circuit according to claim 1 , wherein the source terminal of the amplifier transistor is connected to a bottom terminal of the amplifier transistor.
6. The sample-and-hold circuit according to claim 1 , further comprising a clamping transistor,
wherein a drain terminal of the clamping transistor is connected to the source terminal of the amplifier transistor, the resistor, and the first switch.
7. The sample-and-hold circuit according to claim 6 , wherein a drain terminal of the amplifier transistor and a source terminal of the clamping transistor are connected to a current source.
8. The sample-and-hold circuit according to claim 6 , wherein a gate terminal of the clamping transistor is configured to receive a clamping voltage that is switched between a first level and a second level.
9. The sample-and-hold circuit according to claim 6 , wherein the amplifier transistor is an NMOS transistor, and the clamping transistor is a PMOS transistor.
10. The sample-and-hold circuit according to claim 1 , wherein a drain terminal of the amplifier transistor is connected to an output node of the sample-and-hold circuit.
11. An image sensor, comprising:
a pixel circuit configured to configured to convert incident light into an analog signal; and
a sample-and-hold circuit configured to receive the analog signal, the sample-and-hold-circuit including:
an amplifier transistor;
a resistor connected between a source terminal of the amplifier transistor and a predetermined voltage;
a first switch connected in parallel with the resistor; and
a second switch connected between a gate terminal of the amplifier transistor and the predetermined voltage.
12. The image sensor according to claim 11 , wherein
in a case where the first switch is closed and the second switch is open, the amplifier transistor is in an inversion mode, and
in a case where the first switch is open and the second switch is closed, the amplifier transistor is in an accumulation mode.
13. The image sensor according to claim 12 , wherein the first switch and the second switch are controlled such that when the first switch is open, the second switch is closed; and
when the first switch is closed, the second switch is opened.
14. The image sensor according to claim 12 , wherein the amplifier transistor is switched between the inversion mode and the accumulation mode in an alternating manner.
15. The image sensor according to claim 11 , wherein the source terminal of the amplifier transistor is connected to a bottom terminal of the amplifier transistor.
16. The image sensor according to claim 11 , further comprising a clamping transistor,
wherein a drain terminal of the clamping transistor is connected to the source terminal of the amplifier transistor, the resistor, and the first switch.
17. The image sensor according to claim 16 , wherein a drain terminal of the amplifier transistor and a source terminal of the clamping transistor are connected to a current source.
18. The image sensor according to claim 16 , wherein a gate terminal of the clamping transistor is configured to receive a clamping voltage that is switched between a first level and a second level.
19. The image sensor according to claim 16 , wherein the amplifier transistor is an NMOS transistor, and the clamping transistor is a PMOS transistor.
20. The image sensor according to claim 11 , wherein a drain terminal of the amplifier transistor is connected to an output node of the sample-and-hold circuit.