Dynamic adjustment of memory cell digit line capacitance
Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A ferroelectric memory cell may be used to store a logic state. The capacitance of a digit line of the ferroelectric memory cell may be dynamically increased prior to, and during a portion of, a read operation used to determine a stored logic state of the cell. The capacitance may be increased by leveraging intrinsic capacitance of digit lines of the array—e.g., by shorting one digit line to another digit line. Increasing the capacitance of the digit line may increase the signal on the digit line that is sensed during the read operation.
1. An apparatus, comprising:
a first memory cell coupled with a first access line;
a second memory cell coupled with a second access line different than the first access line, wherein the second access line is shorted with the first access line;
a selection component coupled with the first access line, wherein the selection component is configured to determine a voltage of the first access line and isolate the first access line from the second access line based at least in part on the determined voltage relative to a threshold value.
2. The apparatus of claim 1 , further comprising:
a sense component coupled with the first access line, wherein the sense component is configured to determine a reference voltage of at least one of the first memory cell, the second memory cell, or both.
3. The apparatus of claim 1 , further comprising:
a switching component coupled with each of the first access line and the second access line.
4. The apparatus of claim 1 , wherein the second memory cell comprises an inactive memory cell, wherein the second memory cell is inactive based at least in part on the second access line being inactive.
5. The apparatus of claim 1 , further comprising:
a plate coupled with the first memory cell;
a first voltage source coupled with the plate; and
a second voltage source coupled with the first access line, wherein the second voltage source is different than the first voltage source.
6. The apparatus of claim 5 , wherein the second voltage source is a virtual ground.
7. The apparatus of claim 1 , wherein the selection component is further configured to compare the determined voltage and the threshold value.
8. The apparatus of claim 1 , further comprising:
a third voltage source coupled with the second access line; and
a fourth voltage source coupled with the second access line, wherein the fourth voltage source is different than the third voltage source.
9. An apparatus, comprising:
a memory cell coupled with a first access line;
a sense component coupled with the first access line;
a reference component coupled with the sense component, wherein the reference component is configured to provide a reference voltage to the sense component, wherein the sense component is configured to determine a logic state of the memory cell based at least in part on the reference voltage; and
a capacitor coupled with the first access line, wherein the capacitor is configured to receive a voltage applied by a memory controller based at least in part on the sense component determining a first logic state of the memory cell.
10. The apparatus of claim 9 , further comprising:
a voltage source coupled with the first access line, wherein the voltage source is configured to initialize the first access line to a first voltage.
11. The apparatus of claim 10 , wherein the voltage source coupled with the first access line is a virtual ground.
12. The apparatus of claim 9 , wherein the memory controller is configured to activate the capacitor coupled with the first access line based at least in part on the sense component determining the first logic state of the memory cell.
13. The apparatus of claim 12 , wherein the capacitor is configured to be deactivated based at least in part on the sense component determining a second logic state of the memory cell, wherein the second logic state is different than the first logic state.
14. The apparatus of claim 13 , wherein the memory controller is configured to deactivate the capacitor based at least in part on the sense component determining the second logic state of the memory cell.
15. The apparatus of claim 9 , wherein the capacitor is coupled with the first access line through a switching component.
16. An apparatus, comprising:
a first memory cell coupled with a first access line;
a second memory cell coupled with a second access line different than the first access line;
a selection component coupled with the first access line; and
a memory controller coupled with the first memory cell, wherein the memory controller is operable to:
short the first access line with the second access line;
determine a voltage of the first access line; and
isolate the first access line from the second access line based at least in part on the determined voltage of the first access line exceeding a threshold value.
17. The apparatus of claim 16 , further comprising:
a sense component coupled with the first access line and the memory controller, wherein the memory controller is further operable to:
activate the sense component; and
determine a reference voltage of the second access line based at least in part on activating the sense component.
18. The apparatus of claim 16 , further comprising:
a first voltage source coupled with the first access line through a first switching component, wherein the memory controller is further operable to activate the first switching component based at least in part on the determined voltage of the first access line.
19. The apparatus of claim 18 , further comprising:
a second voltage source coupled with the first access line through a second switching component, wherein the memory controller is further operable to activate the second switching component based at least in part on the determined voltage of the first access line.
20. The apparatus of claim 19 , wherein at least one of the first voltage source or the second voltage source is a virtual ground.