System and method for controlling at least one switching device, especially for use in aircraft

1. A system, especially for use in aircraft, for controlling at least one switching device ( 5 , 5 b , 5 n ) able to open or close a connection between at least one power source and at least one supplied device, and means for measuring a state of a power supply channel, the system being characterized in that it comprises:

at least two microcontrollers ( 1 a , 1 b ) each able to emit a command directed to each of the at least one switching devices ( 5 , 5 b , 5 n ) of a power supply channel, the at least two microcontrollers ( 1 a , 1 b ) being couplable to at least one portion of the means for measuring the state of the power supply channel, and

a means ( 14 , 14 b , 14 n ) for determining a command to be transmitted, able to determine the command to be transmitted to each of the at least one switching devices ( 5 , 5 b , 5 n ) from the commands emitted by each of the at least two microcontrollers ( 1 a , 1 b ) and directed to each of the at least one switching devices ( 5 , 5 b , 5 n ).

2. The system according to claim 1 , in which the means ( 14 , 14 b , 14 n ) for determining the command to be transmitted comprise three inputs carrying a command signal originating from three microcontrollers:

an input carrying a command signal of a first microcontroller ( 1 a ) being connected to a NOT logic gate ( 31 ),

an input carrying a command signal of a second microcontroller ( 1 b ) and an input carrying the command signal of a third microcontroller ( 1 c ) being connected to a first AND logic gate ( 32 ),

the NOT logic gate ( 31 ) and the first AND logic gate ( 32 ) being connected to a second AND logic gate ( 33 ),

the input carrying the command signal of the second microcontroller ( 1 b ) and the input carrying the command signal of the third microcontroller ( 1 c ) being connected to a first OR logic gate ( 34 ),

the input carrying the command signal of the first microcontroller ( 1 a ) and the first OR logic gate ( 34 ) being connected to a third AND logic gate ( 35 ),

the second AND logic gate ( 33 ) and the third AND logic gate ( 35 ) being connected to a second OR logic gate ( 36 ), and

an output of the second OR logic gate ( 36 ) being connected to an output of the means ( 14 , 14 b , 14 n ) for determining the command to be transmitted.

3. The system according to claim 1 , in which the means ( 14 , 14 b , 14 n ) for determining the command to be transmitted comprises four inputs connected pairwise to a first microcontroller and a second microcontroller ( 1 a , 1 b ),

the four inputs carrying two command signals each originating from one microcontroller, and two validity signals, each also originating from one microcontroller,

the second microcontroller ensuring the redundancy of the first microcontroller,

an input carrying a command signal of the first microcontroller ( 1 a ) and an input carrying the validity signal of the first microcontroller ( 1 a ) being connected to a first NAND logic gate ( 15 ),

an input carrying a command signal of the second microcontroller ( 1 b ) and an input carrying a validity signal of the second microcontroller ( 1 b ) being connected to a second NAND logic gate ( 16 ),

the input carrying the validity signal of the first microcontroller ( 1 a ) and the second NAND logic gate ( 16 ) being connected to an OR logic gate ( 17 ), and

the first NAND logic gate ( 15 ) and the OR logic gate ( 17 ) being connected to a third NAND logic gate ( 18 ), an output of the third NAND logic gate ( 18 ) being connected to an output of the means ( 14 ) for determining the command to be transmitted.

4. The system according to claim 1 , in which the means ( 14 , 14 b , 14 n ) for determining the command to be transmitted comprises four inputs connected pairwise to a first microcontroller and a second microcontroller ( 1 a , 1 b ),

the four inputs carrying two command signals each originating from one microcontroller, and two validity signals, each also originating from one microcontroller,

the second microcontroller ensuring the redundancy of the first microcontroller,

an input carrying a command signal of the first microcontroller ( 1 a ) and an input carrying a validity signal of the first microcontroller ( 1 a ) are connected to a first NAND logic gate ( 19 ),

an input carrying a command signal of the second microcontroller ( 1 b ) and an input carrying a validity signal of the second microcontroller ( 1 b ) are connected to a second NAND logic gate ( 20 ),

the input carrying the validity signal of the first microcontroller ( 1 a ) and the second NAND logic gate ( 20 ) are connected to a first OR logic gate ( 21 ),

the first NAND logic gate ( 19 ) and the first OR logic gate ( 21 ) are connected to a third NAND logic gate ( 22 ),

the input carrying the command signal of the first microcontroller ( 1 a ) and the input carrying the command signal of the second microcontroller ( 1 b ) being connected to a second exclusive OR logic gate ( 23 ),

the input carrying the validity signal of the first microcontroller ( 1 a ) and the input carrying the validity signal of the second microcontroller ( 1 b ) being connected to a fourth AND logic gate ( 24 ),

the second exclusive OR logic gate ( 23 ) and the fourth AND logic gate ( 24 ) being connected to a fifth AND logic gate ( 25 ),

the third NAND logic gate ( 22 ) and the fifth AND logic gate ( 25 ) being connected to a sixth NAND logic gate ( 26 ), and the third NAND logic gate ( 22 ) being connected to a NOT logic gate ( 27 ),

the NOT logic gate ( 27 ) and the fifth AND logic gate ( 25 ) being connected to a seventh NAND logic gate ( 28 ),

the sixth NAND logic gate ( 26 ) being connected to a first input of an eighth NAND logic gate ( 29 ),

the seventh NAND logic gate ( 28 ) being connected to the second input of a ninth NAND logic gate ( 30 ), an output of the ninth NAND logic gate ( 30 ) being connected to a second input of the eighth NAND logic gate ( 29 ), an output of the eighth NAND logic gate ( 29 ) being connected to a first input of the ninth NAND logic gate ( 30 ), and

the output of the eighth NAND logic gate ( 29 ) also being connected to an output of the means ( 14 ) for determining the command to be transmitted.

5. Use of the system according to claim 1 , in a power distribution system of an aircraft comprising at least one power supply channel comprising at least one switching device ( 5 , 5 b , 5 n ).

6. A method, especially for use in aircraft, for controlling at least one switching device ( 5 , 5 b , 5 n ) able to open or close a connection between at least one power source and at least one supplied device, by means of a control system comprising:

means for measuring a state of the connection,

at least two microcontrollers ( 1 a , 1 b ) each able to emit a command directed to each of the at least one switching devices ( 5 , 5 b , 5 n ), the at least two microcontrollers ( 1 a , 1 b ) being connected to at least one portion of the means for measuring the state of the connection, and

characterized in that it comprises a step in which the command transmitted to each switching device ( 5 , 5 b , 5 n ) is determined from the commands emitted by the microcontrollers and directed to each of the at least one switching devices ( 5 , 5 b , 5 n ).

7. The method according to claim 6 , in which a command corresponding to the command received from most of the microcontrollers ( 1 a , 1 b , 1 c ) is transmitted as an output, the control system comprising an uneven number of microcontrollers ( 1 a , 1 b , 1 c ) higher than three.

8. The method according to claim 6 , in which each of the at least two microcontrollers ( 1 a , 1 b ) emits a command able to take a first command value or a second command value and a validity value able to take a first validity value if the command is judged valid by a first microcontroller of the at least two microcontrollers and a second validity value if the command is judged invalid by the first microcontroller,

a second microcontroller ensuring the redundancy of the first microcontroller,

if the commands received as inputs are accompanied by different validity values, the command received as input for which the validity value corresponds to the first command value is transmitted,

or, if different commands received as inputs are accompanied by validity values corresponding to the second validity value, the first command value is transmitted,

or, if identical commands received as inputs are accompanied by validity values corresponding to the second validity value, the first command value is transmitted.

9. The method according to claim 8 , in which if different commands received as inputs are accompanied by validity values corresponding to the first command value, the command transmitted by the first microcontroller is transmitted.

10. The method according to claim 8 , in which if different commands received as inputs are accompanied by validity values corresponding to the first command value, the command received beforehand is transmitted.

11. Use of the method according to claim 6 , to control a power distribution system of an aircraft comprising at least one power supply channel comprising at least one switching device ( 5 , 5 b , 5 n ).