Method of forming a P-type ohmic contact in group-III nitride semiconductors
There is a problem that even if impurities are made to thermally diffuse in a temperature range of 700° C.-1150° C., a good ohmic contact cannot be formed in a p-type group-III nitride semiconductor layer. Provided is a semiconductor device manufacturing method having a group-III nitride semiconductor substrate and a p-type group-III nitride semiconductor layer on the group-III nitride semiconductor substrate, including forming a magnesium containing layer on and in direct contact with the p-type group-III nitride semiconductor layer; and annealing the p-type group-III nitride semiconductor layer at a temperature more than or equal to 1300° C. to form a p + -type region which contains magnesium as an impurity in the p-type group-III nitride semiconductor layer located immediately below the magnesium containing layer.
1. A semiconductor device manufacturing method having a group-III nitride semiconductor substrate and a p-type group-III nitride semiconductor layer on the group-III nitride semiconductor substrate, comprising:
forming a magnesium containing layer to be on and in direct contact with the p-type group-III nitride semiconductor layer; and
annealing the p-type group-III nitride semiconductor layer at a temperature more than or equal to 1300° C. to form a p + -type region which contains magnesium as an impurity in the p-type group-III nitride semiconductor layer located immediately below the magnesium containing layer.
2. The semiconductor device manufacturing method according to claim 1 , wherein
in the annealing, the p-type group-III nitride semiconductor layer is annealed at a temperature more than or equal to 1500° C.
3. The semiconductor device manufacturing method according to claim 1 , wherein
in the annealing, the p-type group-III nitride semiconductor layer is annealed at a temperature less than or equal to 2000° C.
4. The semiconductor device manufacturing method according to claim 1 , further comprising
after the forming a magnesium containing layer and before the forming a p + -type region, forming a protective film on the p-type group-III nitride semiconductor layer and the magnesium containing layer.
5. The semiconductor device manufacturing method according to claim 4 , wherein
the protective film covers an upper surface and side surfaces of the magnesium containing layer and an upper surface of the p-type group-III nitride semiconductor layer.
6. The semiconductor device manufacturing method according to claim 4 , wherein
the protective film has any one of aluminum nitride, boron nitride and other high melting point materials.
7. The semiconductor device manufacturing method according to claim 4 further comprising:
after the forming a p + -type region,
removing the protective film; and
removing the magnesium containing layer.
8. The semiconductor device manufacturing method according to claim 1 , wherein
the group-III nitride semiconductor substrate has a threading dislocation density less than 10 7 cm −2 .
9. The semiconductor device manufacturing method according to claim 1 , wherein
the p + -type region has a magnesium concentration more than or equal to 1E+18 cm −3 and less than or equal to 1E+21 cm −3 .
10. The semiconductor device manufacturing method according to claim 1 , further comprising:
before the forming a p-type group-III nitride semiconductor layer, forming an n-type group-III nitride semiconductor layer between the group-III nitride semiconductor substrate and the p-type group-III nitride semiconductor layer;
after the forming a p-type group-III nitride semiconductor layer, forming an n + -type group-III nitride semiconductor layer on the p-type group-III nitride semiconductor layer;
after the forming an n + -type group-III nitride semiconductor layer and before the forming a magnesium containing layer, forming a pair of n + -type regions on a further inner side than the pair of p + -type regions in a cross section perpendicular to a front surface of the semiconductor layer by partially removing the n + -type group-III nitride semiconductor layer;
after the forming a p + -type region, forming an n-type region in the p-type group-III nitride semiconductor layer by implanting n-type impurities into a position in the p-type group-III nitride semiconductor layer, the position being between the pair of n + -type regions and other than the p + -type region;
after the forming an n-type region, forming a gate insulating film on the n-type region;
after the forming a gate insulating film, forming a gate electrode to be on and in direct contact with the gate insulating film;
after the forming an n-type region, forming a source electrode to electrically connect to the pair of n + -type regions and the p + -type region; and
after the forming an n-type region, forming a drain electrode to be under and in direct contact with the group-III nitride semiconductor substrate.