Method of semiconductor integrated circuit fabrication
A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a substrate and depositing a conductive layer on the substrate. A patterned hard mask and a catalyst layer are formed on the conductive layer. The method further includes growing a plurality of carbon nanotubes (CNTs) from the catalyst layer and etching the conductive layer by using the CNTs and the patterned hard mask as an etching mask to form metal features.
1. A method comprising:
forming a conductive layer on a substrate;
forming a catalyst layer on the conductive layer;
forming a plurality of carbon nanotubes (CNTSs) from the catalyst layer;
patterning the conductive layer by using the plurality of CNTs as a mask to form conductive features; and
forming a dielectric layer directly on the plurality of CNTs.
2. The method of claim 1 , wherein forming the dielectric layer directly on the plurality of CNTs includes forming the dielectric layer directly on the patterned conductive layer.
3. The method of claim 1 , further comprising forming a patterned material layer over the conductive layer, the patterned material layer defining an opening, and
wherein forming the catalyst layer on the conductive layer includes forming the catalyst layer in the opening defined by the patterned material layer.
4. The method of claim 3 , wherein the patterned material layer includes a photoresist material.
5. The method of claim 3 , further comprising removing the patterned material layer prior to forming the plurality of CNTSs from the catalyst layer.
6. The method of claim 1 , further comprising forming a patterned hard mask layer over the conductive layer, and
wherein patterning the conductive layer by using the plurality of CNTs as a mask to form conductive features includes patterning the conductive layer by using the patterned hard mask layer as a mask.
7. The method of claim 1 , wherein forming the catalyst layer on the conductive layer includes forming the catalyst layer directly on the conductive layer such that the catalyst layer physically contacts the conductive layer.
8. A method comprising:
forming a conductive layer on a substrate;
forming a patterned material layer on the conductive layer, the patterned material layer defining an opening that exposes a portion of the conductive layer;
forming a catalyst layer on the exposed portion of the conductive layer;
removing the patterned material layer;
forming a plurality of carbon nanotubes (CNTs) from the catalyst layer; and
patterning the conductive layer by using the plurality of CNTs as a mask to form conductive features.
9. The method of claim 8 , further comprising forming a patterned hard mask layer on the conductive layer prior to forming the patterned material layer on the conductive layer.
10. The method of claim 9 , wherein forming the patterned material layer on the conductive layer includes forming the patterned material layer directly on the patterned hard mask layer.
11. The method of claim 10 , wherein the patterned hard mask layer defines another opening, and
wherein forming the patterned material layer on the conductive layer includes forming the patterned material layer within the another opening.
12. The method of claim 8 , wherein removing the patterned material layer occurs prior to forming the plurality of CNTs from the catalyst layer.
13. The method of claim 8 , wherein patterning the conductive layer by using CNTs as the mask to form conductive features includes performing a dry etch process.
14. The method of claim 8 , further comprising forming a dielectric layer directly on the conductive features and the plurality of CNTs.
15. A method comprising:
forming a metal layer on a substrate;
forming a patterned first material layer on the metal layer, the patterned first material layer defining an opening that exposes a portion of the metal layer;
forming a patterned second material layer on the patterned first material layer and within the opening;
forming a catalyst layer on the exposed portion of the metal layer;
removing the patterned second material layer;
forming a plurality of carbon nanotubes (CNTs) from the catalyst layer; and
etching the metal layer by using the plurality of CNTs as a mask.
16. The method of claim 15 , wherein the patterned first material layer is formed of a different material than the patterned second material layer.
17. The method of claim 15 , wherein removing the patterned second material layer exposes the portion of the metal layer.
18. The method of claim 15 , wherein forming the patterned first material layer on the metal layer includes forming the patterned first material layer directly on the metal layer such that the patterned first material layer physically contacts the metal layer,
wherein forming the patterned second material layer on the patterned first material layer includes forming the patterned second material layer directly on the patterned first material layer such that the patterned second material layer physically contacts the patterned first material layer, and
wherein forming the catalyst layer on the exposed portion of the metal layer includes forming the catalyst layer directly on the exposed portion of the metal layer such that the catalyst layer physically contacts the exposed portion of the metal layer.
19. The method of claim 15 , wherein etching the metal layer by using the plurality of CNTs as a mask includes etching the metal layer by using the patterned first material layer as a mask.
20. The method of claim 15 , wherein etching the metal layer by using the plurality of CNTs as the mask exposes a portion of the substrate.