Devices and methods for a power transistor having a schottky or schottky-like contact
Devices, structures, and methods thereof for providing a Schottky or Schottky-like contact as a source region and/or a drain region of a power transistor are disclosed. A power transistor structure comprises a substrate of a first dopant polarity, a drift region formed on or within the substrate, a body region formed on or within the drift region, a gate structure formed on or within the substrate, a source region adjacent to the gate structure, a drain region formed adjacent to the gate structure. At least one of the source region and the drain region is formed from a Schottky or Schottky-like contact substantially near a surface of the substrate, comprising a silicide layer and an interfacial dopant segregation layer. The Schottky or Schottky-like contact is formed by low-temperature annealing a dopant segregation implant in the source and/or drain region.
1. A lateral power transistor structure, comprising:
a substrate of a first dopant polarity;
a drift region of a second dopant polarity formed on or within the substrate;
a body region of a first dopant polarity formed on or within the drift region;
a gate dielectric film in contact with the substrate;
a gate structure abutting the gate dielectric film;
a source region outside the gate structure;
a drain region formed on the substrate;
wherein periodic and non-continuous body contacts are integrated into the source region; and
wherein the source region is a Schottky contact formed substantially near a surface of the substrate for eliminating a parasitic bipolar junction transistor for providing an improved safe operating area, reducing a specific on-state resistance of the lateral power transistor structure, and/or reducing a die size of the lateral power transistor structure.
2. The lateral power transistor structure of claim 1 , wherein the Schottky or Schottky like contact comprises a silicide layer and an interfacial dopant segregation layer.
3. The lateral power transistor structure of claim 1 , further comprising a spacer abutting a sidewall of the gate structure.
4. The lateral power transistor structure of claim 3 , wherein the spacer is asymmetric between the source region and the drain region.
5. The lateral power transistor structure of claim 3 , wherein a width of the spacer is adjustable for electrical coupling optimization.