Fan-out package structure and method

1. A method comprising:

attaching a semiconductor structure on a carrier, wherein the semiconductor structure comprises a plurality of connectors;

depositing a molding compound layer over the carrier, wherein the semiconductor structure is embedded in the molding compound layer;

depositing a first photo-sensitive material layer on the molding compound layer;

exposing the first photo-sensitive material layer to light according to a first pattern;

depositing a second photo-sensitive material layer on the first photo-sensitive material layer;

exposing the second photo-sensitive material layer to light according to a second pattern;

developing the first photo-sensitive material layer and the second photo-sensitive material layer to form a plurality of openings, wherein a first portion of an opening of the plurality of openings is formed in the first photo-sensitive material layer and based upon the first pattern, and a second portion of the opening is formed in the second photo-sensitive material layer and based upon the second pattern, and wherein a width of the first portion is different from a width of the second portion;

filling the plurality of openings with a conductive material to form a via in the first portion and a first redistribution layer in the second portion; and

forming a plurality of bumps over the first redistribution layer.

2. The method of claim 1 , further comprising:

after the step of depositing the molding compound layer over the carrier, applying a grinding process to the molding compound layer until a top surface of the semiconductor structure is exposed.

3. The method of claim 1 , further comprising:

prior to the step of filling the plurality of openings with the conductive material, forming a photoresist layer on a top surface of the second photo-sensitive material layer.

4. The method of claim 3 , wherein:

a sidewall of the photoresist layer is vertically aligned with a sidewall of one opening of the plurality of openings; and

a thickness of the photoresist layer is greater than 5 um.

5. The method of claim 3 , wherein:

after the step of filling the plurality of openings with the conductive material, a top surface of the first redistribution layer is substantially level with a bottom surface of the photoresist layer.

6. The method of claim 1 , further comprising:

forming a second redistribution layer over the first redistribution layer; and

forming a third redistribution layer over the second redistribution layer.

7. The method of claim 1 , further comprising:

forming a plurality of under bump metallization structures over the first redistribution layer; and

forming the plurality of bumps on the plurality of under bump metallization structures.

8. The method of claim 1 , further comprising:

forming a seed layer in the plurality of openings prior to the step of filling the plurality of openings with the conductive material.

9. The method of claim 1 , further comprising:

after the step of forming a plurality of bumps over the first redistribution layer, separating the carrier from the semiconductor structure.

10. A method comprising:

attaching a semiconductor structure on a carrier, wherein the semiconductor structure comprises a connector, and wherein a top surface of the connector is substantially level with a top surface of the semiconductor structure;

depositing a molding compound layer over the carrier, wherein the semiconductor structure is embedded in the molding compound layer;

exposing a first photo-sensitive material layer and a second photo-sensitive material layer to light;

developing the first photo-sensitive material layer and the second photo-sensitive material layer to form an opening having a first portion in the first photo-sensitive material layer and a second portion in the second photo-sensitive material layer, wherein a width of the second portion is greater than a width of the first portion;

filling the opening with a conductive material to form a via in the first photo-sensitive material layer and a redistribution layer in the second photo-sensitive material layer; and

forming a bump over the redistribution layer.

11. The method of claim 10 , further comprising:

depositing the first photo-sensitive material layer on the molding compound layer;

exposing the first photo-sensitive material layer to light according to a first pattern;

depositing a second photo-sensitive material layer on the first photo-sensitive material layer; and

exposing the second photo-sensitive material layer to light according to a second pattern.

12. The method of claim 10 , further comprising:

forming an under bump metallization structure over the redistribution layer; and

forming the bump over the under bump metallization structure.

13. The method of claim 10 , wherein:

a surface of the connector is in direct contact with a surface of the via.

14. The method of claim 10 , further comprising:

prior to the step of filling the opening with the conductive material, forming a photoresist layer on a top surface of the second photo-sensitive material layer.

15. The method of claim 14 , wherein:

a sidewall of the photoresist layer is vertically aligned with a sidewall of the opening; and

a thickness of the photoresist layer is greater than 5 um.

16. A method comprising:

attaching a semiconductor structure on a carrier;

depositing a molding compound layer over the carrier, wherein the semiconductor structure is embedded in the molding compound layer;

applying a grinding process to the molding compound layer until a top surface of the semiconductor structure is exposed;

depositing a first photo-sensitive material layer over the molding compound layer and exposing the first photo-sensitive material layer to light;

depositing a second photo-sensitive material layer over the first photo-sensitive material layer and exposing the second photo-sensitive material layer to light;

developing the first photo-sensitive material layer and the second photo-sensitive material layer to form an opening having a first portion in the first photo-sensitive material layer and a second portion in the second photo-sensitive material layer; and

filling the opening with a conductive material to form a via in the first portion and a redistribution layer in the second portion.

17. The method of claim 16 , wherein:

the semiconductor structure comprises a connector having a top surface substantially level with the top surface of the semiconductor structure; and

a width of the second portion is greater than a width of the first portion.

18. The method of claim 17 , wherein:

after developing the first photo-sensitive material layer and the second photo-sensitive material layer to form the opening, at least a portion of the top surface of the connector is exposed.

19. The method of claim 16 , further comprising:

forming a bump over the redistribution layer.

20. The method of claim 16 , further comprising:

separating the carrier from the semiconductor structure.