Semiconductor system and device
A 3D IC device including: a first semiconductor layer including first mono-crystallized transistors, where the first mono-crystallized transistors are interconnected by at least one metal layer including aluminum or copper; a second layer including second mono-crystallized transistors and overlaying the at least one metal layer, where the at least one metal layer is in-between the first semiconductor layer and the second layer; a global power grid to distribute power to the device overlaying the second layer; and a local power grid to distribute power to the first mono-crystallized transistors, where the global power grid is connected to the local power grid by a plurality of through second layer vias, and where the vias have a radius of less than 150 nm.
1. A 3D IC device comprising:
a first semiconductor layer comprising first mono-crystallized transistors,
wherein said first mono-crystallized transistors are interconnected by at least one metal layer comprising a majority of aluminum or copper;
a second layer comprising second mono-crystallized transistors and overlaying said at least one metal layer,
wherein said at least one metal layer is in-between said first semiconductor layer and said second layer;
a global power grid to distribute power to said device overlaying said second layer; and
a local power grid to distribute power to said first mono-crystallized transistors,
wherein said global power grid is connected to said local power grid by a plurality of through second layer vias, and
wherein said vias have a radius of less than 150 nm.
2. The 3D IC device according to claim 1 , further comprising:
a first alignment mark and a second alignment mark; and
wherein said first layer comprises said first alignment mark and said second layer comprises said second alignment mark,
wherein at least one of said vias is aligned to said first alignment mark and said second alignment mark.
3. The 3D IC device according to claim 1 ,
wherein said second mono-crystallized transistors comprise horizontally oriented transistors.
4. The 3D IC device according to claim 1 ,
wherein said global power grid provides a network thermal path from at least one of said second mono-crystallized transistors to an external surface of said device.
5. The 3D IC device according to claim 1 , further comprising:
a heat spreader layer disposed between said second layer and said at least one metal layer.
6. The 3D IC device according to claim 1 , further comprising:
a plurality of thermal paths between said second mono-crystallized transistors and a heat removal apparatus,
wherein at least one of said plurality of thermal paths comprises a thermal contact adapted to conduct heat and not conduct electricity.
7. The 3D IC device according to claim 1 ,
wherein at least one of said second mono-crystallized transistors is one of:
(i) a recessed-channel transistor (RCAT);
(ii) a junction-less transistor;
(iii) a replacement-gate transistor; or
(iv) a Finfet transistor.
8. The 3D IC device comprising:
a first semiconductor layer comprising first mono-crystallized transistors,
wherein said first mono-crystallized transistors are interconnected by at least one metal layer comprising a majority of aluminum or copper;
a second layer comprising second mono-crystallized transistors and overlaying said at least one metal layer;
wherein said at least one metal layer is disposed between said first semiconductor layer and said second layer, and
a global power grid to distribute power to said device overlaying said second layer; and
a local power grid to distribute power to said first mono-crystallized transistors,
wherein said global power grid is connected to said local power grid by a plurality of through second layer vias,
wherein said vias have a radius of less than 150nm, and
wherein said global power grid provides a network thermal path from at least one of said second mono-crystallized transistors to an external surface of said device.
9. The 3D IC device according to claim 8 ,
wherein said second mono-crystallized transistors comprise horizontally oriented transistors.
10. A 3D IC device comprising:
a first semiconductor layer comprising first mono-crystallized transistors,
wherein said first mono-crystallized transistors are interconnected by at least one metal layer comprising a majority of aluminum or copper;
a second layer comprising second mono-crystallized transistors and overlaying said at least one metal layer;
wherein said at least one metal layer is disposed between said first semiconductor layer and said second layer, and
a global power grid to distribute power to said device overlaying said second layer; and
a local power grid to distribute power to said first mono-crystallized transistors,
wherein said global power grid is connected to said local power grid by a plurality of through second layer vias,
wherein said vias have a radius of less than 150 nm, and
wherein said global power grid provides a network thermal path from at least one of said second mono-crystallized transistors to an external surface of said device.
11. The 3D IC device according to claim 10 , further comprising:
a heat spreader layer disposed between said second layer and said at least one metal layer.
12. The 3D IC device according to claim 10 , further comprising:
a plurality of thermal paths between said second mono-crystallized transistors and a heat removal apparatus,
wherein at least one of said plurality of thermally conductive paths comprises a contact adapted to conduct heat and not conduct electricity.
13. The 3D IC device according to claim 10 ,
wherein at least one of said second mono-crystallized transistors is one of:
(i) a recessed-channel transistor (RCAT);
(ii) a junction-less transistor;
(iii) a replacement-gate transistor; or
(iv) a Finfet transistor.
14. A 3D IC device comprising:
a first semiconductor layer comprising first mono-crystallized transistors,
wherein said first mono-crystallized transistors are interconnected by at least one metal layer comprising a majority of aluminum or copper; and
a second layer comprising second mono-crystallized transistors and overlaying said at least one metal layer,
wherein said at least one metal layer is in-between said first semiconductor layer and said second layer, and
a global power grid to distribute power to said device overlaying said second layer; and
a local power grid to distribute power to said first mono-crystallized transistors,
wherein said global power grid is connected to said local power grid by a plurality of through second layer vias,
wherein said vias have a radius of less than 150 nm, and
wherein at least one of said second mono-crystallized transistors is one of:
(i) a recessed-channel transistor (RCAT);
(ii) a junction-less transistor;
(iii) a replacement-gate transistor; or
(iv) a Finfet transistor.
15. The 3D IC device according to claim 14 , further comprising:
a heat spreader layer between said second layer and said at least one metal layer.
16. The 3D IC device according to claim 14 , further comprising:
a first alignment mark and a second alignment mark; and
wherein said first layer comprises said first alignment mark and said second layer comprises said second alignment mark,
wherein at least one of said vias is aligned to said first alignment mark and said second alignment mark.
17. The 3D IC device according to claim 14 ,
wherein said second mono-crystallized transistors comprise horizontally oriented transistors.
18. The 3D IC device according to claim 14 ,
wherein said global power grid provides a network thermal path from at least one of said second mono-crystallized transistors to an external surface of said device.
19. The 3D IC device according to claim 14 , further comprising:
a plurality of thermal paths between said second mono-crystallized transistors and a heat removal apparatus,
wherein at least one of said plurality of thermal paths comprises a thermal contact adapted to conduct heat and not conduct electricity.
20. The 3D IC device according to claim 14 , further comprising:
a back-gate structure for at least one of said second mono-crystallized transistors.