IP Library › Granted Patent US 9,966,473
Granted Patent B2
US 9,966,473 · App. 15/147,279 · Granted May 8, 2018

Manufacturing method of semiconductor device

Inventor: Yuta Endo (Kanagawa, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
H01L29/7869H01L29/24H01L29/66969H01L29/78618H01L29/78696
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,966,473
App. No.
15/147,279
Granted
May 8, 2018
Kind
B2
Abstract

A miniaturized transistor with less variation and highly stable electrical characteristics is provided. Further, high performance and high reliability of a semiconductor device including the transistor are achieved. A semiconductor and a conductor are formed over a substrate, a sacrificial layer is formed over the conductor, and an insulator is formed to cover the sacrificial layer. After that, a top surface of the insulator is removed to expose a top surface of the sacrificial layer. The sacrificial layer and a region of the conductor overlapping with the sacrificial layer are removed, whereby a source region, a drain region, and an opening are formed. Next, a gate insulator and a gate electrode are formed in the opening.

Claims (24)

1. A method for manufacturing a semiconductor device, comprising:

forming a semiconductor over a substrate;

forming a first conductor over the semiconductor;

forming a sacrificial layer over the first conductor;

forming a first insulator so as to cover the semiconductor, the first conductor, and the sacrificial layer;

exposing a top surface of the sacrificial layer;

removing the sacrificial layer to form an opening in the first insulator, so that part of the first conductor is exposed;

forming a pair of electrodes by removing part of the first conductor;

forming a second insulator so as to cover the first insulator and the opening;

forming a second conductor over the second insulator; and

removing part of the second conductor.

2. The method for manufacturing a semiconductor device according to claim 1 ,

wherein the semiconductor is an oxide semiconductor including indium, an element M, and zinc, and

wherein the element M is one of gallium, aluminum, yttrium, and tin.

3. The method for manufacturing a semiconductor device according to claim 1 ,

wherein the first conductor comprises one of a metal film and a metal nitride film, and

wherein each of the metal film and the metal nitride film includes one of molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, and scandium.

4. The method for manufacturing a semiconductor device according to claim 1 , wherein the first conductor comprises a material including one of indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide containing silicon oxide.

5. The method for manufacturing a semiconductor device according to claim 1 , wherein an etching rate of the sacrificial layer is higher than that of the first conductor.

6. The method for manufacturing a semiconductor device according to claim 1 , wherein the sacrificial layer includes one of boron, nitrogen, oxygen, fluorine, silicon, phosphorus, aluminum, titanium, chromium, manganese, cobalt, nickel, copper, zinc, gallium, yttrium, zirconium, molybdenum, ruthenium, silver, indium, tin, tantalum, and tungsten.

7. The method for manufacturing a semiconductor device according to claim 1 , wherein the sacrificial layer comprises one of a silicon film, a chromium film, a molybdenum film, a tungsten film, a zinc oxide film, and a molybdenum oxide film.

8. The method for manufacturing a semiconductor device according to claim 1 , wherein the step of removing the sacrificial layer is performed by a wet etching method.

9. The method for manufacturing a semiconductor device according to claim 1 , wherein the step of exposing the top surface of the sacrificial layer is performed by a chemical mechanical polishing method.

10. The method for manufacturing a semiconductor device according to claim 1 , wherein the step of removing the part of the second conductor is performed by a chemical mechanical polishing method.

Assignments (1)
CORRECTIVE ASSIGNMENT TO CORRECT THE FILING DATE AND THE APPLICATION NUMBER 15142279 NUMBER SHOULD BE 1547279 PREVIOUSLY RECORDED AT REEL: 038791 FRAME: 0246. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Jun 10, 2016
From: ENDO, YUTA
To: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Reel/Frame 038950/0308 →
Priority Claims (1)
JP 2015-096317 · May 11, 2015 · national
Continuity (1)
Related Publication 20160336454A1 · Nov 17, 2016