IP Library › Granted Patent US 9,978,314
Granted Patent B2
US 9,978,314 · App. 15/134,214 · Granted May 22, 2018

Gate driver including a plurality of normal stages and a plurality of dummy stages and display device having the same

Inventors: Jung-Bae Bae (Asan-si, KR); So-Young Lee (Asan-si, KR); Won-Se Lee (Seoul, KR)
Assignee: Samsung Display Co., Ltd.
G09G3/3266G09G3/2085G11C19/28G09G2300/0413G09G2300/0426G09G2310/0262G09G2310/0286G09G2310/08G09G2320/02G09G2320/045G09G2330/08G09G2380/10
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Quick Facts
Patent No.
US 9,978,314
App. No.
15/134,214
Granted
May 22, 2018
Kind
B2
Abstract

A display device includes a display panel having a curved side or a polygonal side, the display panel including a plurality of pixels in a display region, a gate driver including a plurality of normal stages connected to each other for outputting gate signals to the pixels via a plurality of gate lines, and a plurality of dummy stages between some of the normal stages, and a data driver providing data signals to the pixels via a plurality of data lines.

Claims (56)

1. A display device comprising:

a display panel having a non-rectangular-shape, and comprising a plurality of pixels in a display region;

a gate driver comprising:

a plurality of normal stages connected to each other, and configured to output gate signals to the pixels via a plurality of gate lines; and

a plurality of dummy stages between some of the normal stages; and

a data driver configured to provide data signals to the pixels via a plurality of data lines,

wherein each of the normal stages and the dummy stages comprises:

a first power terminal configured to receive a first gate voltage;

an input terminal; and

a clock terminal, and

wherein the first power terminal, the input terminal, and the clock terminal of a same dummy stage of the plurality of dummy stages are directly electrically connected with each other.

2. The display device of claim 1 , wherein each of the normal stages and the dummy stages further comprises an output terminal.

3. The display device of claim 2 , wherein the input terminal and the clock terminal of each of the dummy stages are configured to receive a first gate voltage.

4. The display device of claim 2 , wherein the output terminal of each of the dummy stages is in a floating state.

5. The display device of claim 2 , wherein each of the normal stages and the dummy stages further comprises:

a second power terminal configured to receive a second gate voltage.

6. The display device of claim 1 , wherein a structure of each of the normal stages is the same as a structure of each of the dummy stages.

7. The display device of claim 1 , wherein the normal stages and the dummy stages are arranged in a line corresponding to the non-rectangular shape.

8. The display device of claim 1 , wherein the gate driver is configured to provide scan signals and emission control signals to the pixels as the gate signals.

9. The display device of claim 1 , further comprising:

a complement wiring portion comprising a complement power line surrounding the display region.

10. The display device of claim 9 ,

wherein the pixels are arranged in a first direction and in a second direction,

wherein the display panel further comprises:

a first power line in the display region and extending in the first direction; and

a second power line in the display region and extending in the second direction, and

wherein the complement power line is connected to the first power line and the second power line.

11. The display device of claim 9 , wherein the complement power line comprises:

a curved portion having a second width; and

a straight portion having a first width that is greater than the second width.

12. A display device comprising:

a display panel having a non-rectangular-shape, and comprising a plurality of pixels in a display region;

a gate driver comprising:

a plurality of normal stages connected to each other, and configured to output gate signals to the pixels via a plurality of gate lines; and

a plurality of dummy stages between some of the normal stages; and

a data driver configured to provide data signals to the pixels via a plurality of data lines,

wherein the normal stages and the dummy stages are arranged in a line corresponding to the non-rectangular shape,

wherein the pixels are arranged in a first direction along which the gate lines extend, and in a second direction along which the data lines extend,

wherein a number of the dummy stages between two adjacent normal stages decreases as an angle between the first direction and a tangent of the line corresponding to the non-rectangular shape of the display panel increases, and

wherein the number of the dummy stages between two adjacent normal stages is greater than one when the first angle is smaller than a second angle between the first direction and the second direction.

13. A gate driver for a display panel having a non-rectangular shape, the gate driver comprising:

a plurality of normal stages connected to each other, and configured to respectively output gate signals to a plurality of gate lines; and

a plurality of dummy stages between some of the normal stages,

wherein a number of the dummy stages between two adjacent normal stages decreases as an angle between a first direction along which the gate lines extend and a tangent of the line corresponding to the non-rectangular shape increases.

14. The gate driver of claim 13 , wherein the normal stages and the dummy stages are arranged in a line corresponding to the non-rectangular shape.

15. The gate driver of claim 13 , wherein each of the normal stages and the dummy stages comprises:

a first power terminal configured to receive a first gate voltage;

an input terminal;

a clock terminal; and

an output terminal,

wherein the first power terminal, the input terminal, and the clock terminal of a same dummy stage of the plurality of dummy stages are directly electrically connected with each other.

16. The gate driver of claim 15 , wherein the input terminal and the clock terminal of each of the dummy stages are configured to receive a first gate voltage.

17. The gate driver of claim 15 , wherein the output terminal of each of the dummy stages is in a floating state.

18. The gate driver of claim 15 , wherein each of the normal stages and the dummy stages further comprises:

a second power terminal configured to receive a second gate voltage.

19. The gate driver of claim 13 , wherein a structure of each of the normal stages is the same as a structure of each of the dummy stages.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 20, 2016
From: BAE, JUNG-BAE; LEE, SO-YOUNG; LEE, WON-SE
To: SAMSUNG DISPLAY CO., LTD.
Reel/Frame 038336/0526 →
Priority Claims (1)
KR 10-2015-0147270 · Oct 22, 2015 · national
Continuity (1)
Related Publication 20170116923A1 · Apr 27, 2017