Multi-zone analog-to-digital converter (ADC)
A multi-zone analog-to-digital converter (ADC) is provided that includes a track-and-hold (T/H) stage having a bandwidth of L Hertz (Hz) to accept an analog input signal, a clock input to accept a clock signal with a clock frequency of P Hz, and N deinterleaved signal outputs with a combined bandwidth of M Hz. N×(P/2)=M, L>Q×M, and Q is an integer >1. The T/H stage is able to sample an analog input signal in the Qth Nyquist Zone, where Q is an integer. A quantizer stage has N interleaved signal inputs connected to corresponding T/H stage signal outputs, a clock input to accept the clock signal, and an output to supply a digital output signal having a bandwidth of M Hz. A packaging interface typically connects the T/H stage to the quantizer stage, and has a bandwidth less than the clock frequency.
1. A multi-zone analog-to-digital converter (ADC) comprising:
a track-and-hold (T/H) stage having a signal input with a bandwidth of L Hertz (Hz) to accept an analog input signal, a clock input to accept a clock signal with a clock frequency of P Hz, and N deinterleaved signal outputs with a combined bandwidth of M Hz, where N×(P/2)=M, L>Q×M, and Q is an integer greater than 1; and,
a quantizer stage having N interleaved signal inputs connected to corresponding T/H stage signal outputs, a clock input to accept the clock signal, and an output to supply a digital output signal having a bandwidth of M Hz.
2. The multi-zone ADC of claim 1 wherein the T/H stage samples an analog input signal in the Qth Nyquist Zone.
3. The multi-zone ADC of claim 1 wherein L is at least 105 gigahertz (GHz) and M is about 35 GHz.
4. The multi-zone ADC of claim 1 wherein the T/H stage is fabricated with transistors having a cutoff frequency of greater than L Hz; and,
wherein the quantizer stage is fabricated with transistors having a cutoff frequency greater than M Hz and less than L Hz.
5. The multi-zone ADC of claim 4 wherein the T/H stage is fabricated with silicon/germanium (SiGe) transistors; and,
wherein the quantizer stage is fabricated with CMOS transistors.
6. The multi-zone ADC of claim 1 wherein the quantizer stage further comprises:
N packaging interfaces, each packing interface connecting a T/H stage signal output to a corresponding quantizer stage signal input, and each packaging interface having a bandwidth less than the clock frequency.
7. The multi-zone ADC of claim 1 wherein the T/H stage comprises:
a polyphase sampler having a signal input to accept the analog input signal, a phase input to accept N phases of the clock signal, and outputs to supply N sampled signals, with each sampled signal being sampled at a corresponding clock signal phase;
a delay-locked loop having an input to accept the clock signal, and an output to supply the N phases of the clock frequency;
N output buffers, each output buffer having an input to accept a corresponding sampled signal and an output to supply a corresponding deinterleaved signal output;
wherein the quantizer stage comprises:
a delay-locked loop having an input to accept the clock signal and an output to supply N phases of the clock frequency;
N truncation circuits, each truncation circuit having a signal input to accept a corresponding T/H stage deinterleaved signal output, a phase input to accept a corresponding clock signal phase, and a signal output to supply a corresponding digital value; and,
an interleaver having a signal input to accept the N digital values from the truncation circuits, a clock input to accept the clock signal, and an output to supply the digital output.
8. A multi-zone receiver comprising:
a bandpass filter having an antenna port to accept an analog input signal having a center frequency less than or equal to L Hertz (Hz), and a signal output to supply a filtered signal having a bandwidth of at least M Hz;
a track-and-hold (T/H) stage having a signal input with a bandwidth of at least L Hz to accept the filtered signal, a clock input to accept a clock signal with a clock frequency of P Hz, and N deinterleaved signal outputs with a combined bandwidth of M Hz, where N×(P/2)=M, L>Q×M, and Q is an integer greater than 1; and,
a quantizer stage having N interleaved signal inputs connected to corresponding T/H stage signal outputs, a clock input to accept the clock signal, and an output to supply a digital output signal having a bandwidth of M Hz.
9. The multi-zone receiver of claim 8 wherein the T/H stage samples a filtered input signal in the Qth Nyquist Zone.
10. The multi-zone receiver of claim 8 wherein L is at least 105 gigahertz (GHz) and M is about 35 GHz.
11. The multi-zone receiver of claim 8 wherein the T/H stage is fabricated with transistors having a cutoff frequency of greater than L Hz; and,
wherein the quantizer stage is fabricated with transistors having a cutoff frequency greater than M Hz and less than L Hz.
12. The multi-zone receiver of claim 11 wherein the T/H stage is fabricated with silicon/germanium (SiGe) transistors; and,
wherein the quantizer stage is fabricated with CMOS transistors.
13. The multi-zone receiver of claim 8 wherein the quantizer stage further comprises:
N packaging interfaces, each packaging interface connecting a T/H stage signal output to a corresponding quantizer stage signal input, and each packaging interface having a bandwidth less than the clock frequency.
14. The multi-zone receiver of claim 8 wherein the T/H stage comprises:
a polyphase sampler having a signal input to accept the analog input signal, a phase input to accept N phases of the clock signal, and an output to supply N sampled signals, with each sampled signal being sampled at a corresponding clock signal phase;
a delay-locked loop having an input to accept the clock signal and an output to supply the N phases of the clock frequency;
N output buffers, each output buffer having an input to accept a corresponding sampled signal and an output to supply a corresponding deinterleaved signal output;
wherein the quantizer stage comprises:
a delay-locked loop having an input to accept the clock signal and an output to supply the N phases of the clock frequency;
N truncation circuits, each truncation circuit having a signal input to accept a corresponding T/H stage deinterleaved signal output, a phase input to accept a corresponding clock signal phase, and a signal output to supply a corresponding digital value; and,
an interleaver having a signal input to accept the N digital values from the truncation circuits, a clock input to accept the clock signal, and an output to supply the digital output signal.
15. The multi-zone receiver of claim 8 wherein the bandpass filter has an adjustable bandpass output and a control input to accept a control signal for selecting the bandpass filter center frequency.
16. The multi-zone receiver of claim 15 wherein the bandpass filter accepts a scanning control signal for selectively monitoring frequency bandpass regions of the wireless input signal.
17. The multi-zone receiver of claim 8 further comprising:
(Z-1) additional bandpass filters, each additional bandpass filter having an antenna port to accept the analog input signal and a signal output to supply a corresponding filtered signal having a corresponding bandwidth, where each of the Z bandpass filters supplies a filtered signal in a unique frequency range;
(Z-1) additional T/H stages, each additional T/H stage having a signal input with a bandwidth of at least L Hz to accept a corresponding filtered signal and deinterleaved signal outputs with a corresponding combined bandwidth; and,
(Z-1) additional quantizer stages, each additional quantizer stage having interleaved signal inputs connected to corresponding T/H stage signal outputs and an output to supply a corresponding digital output signal having the corresponding bandwidth, where each of the Z quantizer stages supplies an independent digital output signal.
18. The multi-zone receiver of claim 17 further comprising:
a summer having an input connected to the Z quantizer stages to receive the Z independent digital output signals, and an output to supply an interleaved digital output word.
19. A multi-zone analog-to-digital conversion method comprising:
a track-and-hold (T/H) stage accepting an analog input signal having a bandwidth of M Hertz (Hz) and a center frequency of less than L Hz;
the T/H stage sampling the analog input signal at a rate of N×P Hz, creating samples;
the T/H stage buffering the samples in N deinterleaved buffers, where N×(P/2)=M, where L>Q×M, and where Q is an integer greater than 1;
a quantizer stage quantizing each buffered sample at a rate P Hz, creating quantized samples; and,
the quantizer interleaving the quantized samples at a rate of N×P Hz to create a digital output signal having a bandwidth of M Hz.
20. The method of claim 19 wherein sampling the analog input signal at a rate of N×P Hz includes sampling the analog input signal in the Qth Nyquist Zone.
21. The method of claim 19 wherein L is at least 105 gigahertz (GHz) and M is about 35 GHz.
22. The method of claim 19 wherein sampling the analog input signal at a rate of N×P Hz includes sampling the analog input signal using transistors having a cutoff frequency of greater than L Hz; and,
wherein quantizing each buffered sample includes quantizing the buffered samples using transistors having a cutoff frequency greater than M Hz and less than L Hz.
23. The method of claim 22 wherein sampling the analog input signal includes sampling the analog input signal using silicon/germanium (SiGe) transistors; and,
wherein quantizing the buffered samples includes quantizing the buffered samples using CMOS transistors.
24. The method of claim 19 further comprising:
prior to quantizing the buffered samples, the quantizer stage accepting the buffered samples via a package interface having a bandwidth less than P Hz.
25. The method of claim 19 further comprising:
prior to accepting the analog input signal, a bandpass filter filtering the analog input signal at a center frequency of less than L Hz, with a bandwidth of at least M Hz.
26. A signal distribution system comprising:
an input sampling stage able to sample an analog signal with a bandwidth of M Hertz and a center frequency of greater than M Hertz and less than L Hertz, at a frequency of P Hertz;
a processing stage where the sampled analog signal is distributed into N analog signals, each with a bandwidth of (P/2) Hertz; and,
an output stage with N analog outputs, each with a bandwidth of (P/2) Hertz, where L≥M=N×(P/2).