Metal gate and manufacturing method thereof
The present disclosure provides a semiconductor structure, including an active region with a first surface; an isolated region having a second surface, surrounding the active region, the first surface being higher than the second surface; and a metal gate having a plurality of metal layers disposed over the first surface and the second surface. A ratio of a thinnest portion and a thickest portion of at least one of the plurality of metal layers is greater than about 40%.
1. A method for manufacturing a semiconductor structure, comprising:
defining an active region on a semiconductor substrate by forming an isolated region surrounding the active region;
forming a work function metal layer over the active region and a portion of the isolated region by an RF sputtering operation; and
forming an Al metal layer over the work function metal layer,
wherein the forming the work function metal layer comprises performing a deposition by tuning an impedance associated with the semiconductor substrate from lower than to greater than an impedance of a grounded wall of a sputtering chamber.
2. The method of claim 1 , wherein the tuning the impedance associated with the semiconductor substrate comprises tuning a capacitive element, an inductive element, a resistive element, a geometry of the sputtering chamber, or combinations thereof.
3. The method of claim 1 , wherein the tuning the impedance associated with the semiconductor substrate comprises forming a positive self bias.
4. The method of claim 1 , wherein the tuning the impedance associated with the semiconductor substrate comprises forming a DC bias of from about 35V to about 60V.
5. The method of claim 1 , further comprising:
forming a dummy gate over the active region and the isolated region;
forming conductive regions in the active region by an implantation operation; and
removing the dummy gate by an etching operation before forming the work function metal layer.
6. The method of claim 1 , wherein the defining the active region on a semiconductor substrate comprises a planarization operation to etch back as-deposited dielectric materials.
7. The method of claim 1 , wherein a ratio of a thinnest portion and a thickest portion of the work function metal layer is controlled to be greater than about 40%.
8. A method for manufacturing a semiconductor structure, comprising:
forming an active region in a semiconductor substrate, the active region having a first surface;
forming an isolated region surrounding the active region, the isolated region having a second surface, and the first surface being higher than the second surface;
forming a metal layer over the first surface and the second surface by a sputtering operation, and
tuning an impedance associated with the semiconductor substrate from lower than to greater than an impedance of a grounded wall of a sputtering chamber during the sputtering operation,
wherein a ratio of a thinnest portion and a thickest portion of the metal layer is greater than about 40% by the tuning the impedance.
9. The method of claim 8 , wherein the metal layers is a work function metal layer.
10. The method of claim 8 , wherein the thickest portion is over the first surface.
11. The method of claim 10 , wherein the thinnest portion is at a corner connecting the first surface and the second surface.
12. The method of claim 8 , wherein the metal layer comprises aluminum.
13. The method of claim 8 , further comprising a high k dielectric layer between the metal layer and the active region.
14. The method of claim 8 , a height difference between the first surface and the second surface being in a range of from about 9 nm to about 11 nm.
15. A method for manufacturing a semiconductor structure, comprising:
forming an active region surrounded by an isolated region in a semiconductor substrate, wherein a sidewall and a first surface of the active region protruding from a second surface of the isolated region; and
forming an aluminum-containing layer at least covering the sidewall and the first surface of the active region by a sputtering operation, the sputtering operation comprising tuning an impedance associated with the semiconductor substrate from lower than to greater than an impedance of a grounded wall of a sputtering chamber, the aluminum-containing layer comprising:
a first thickness in proximity to the first surface of the active region;
a second thickness in proximity to a corner connecting the first surface and the sidewall of the active region, and
a thickness ratio of the second thickness and the first thickness is greater than about 40% as a result of the tuning the impedance.
16. The method of claim 15 , wherein the tuning the impedance associated with the semiconductor substrate comprises tuning a capacitive element, an inductive element, a resistive element, a geometry of the sputtering chamber, or combinations thereof.
17. The method of claim 15 , wherein the tuning the impedance associated with the semiconductor substrate comprises forming a DC bias of from about 35V to about 60V.
18. The method of claim 15 , wherein the tuning the impedance associated with the semiconductor substrate comprises forming a positive self bias.
19. The method of claim 15 , wherein the aluminum-containing layer comprises TiAl.