Reference voltage pre-processing circuit and reference voltage pre-processing method for a reference voltage buffer
View Patent ↗Embodiments of the invention relate to a reference voltage pre-processing circuit and method for a reference voltage buffer. The embodiments include a filter to control/reduce the noise and/or interference attached to a reference voltage to be provided to a reference voltage buffer by passing the reference voltage via two transistor in series. Furthermore, the embodiments include an auxiliary voltage circuit which interfaces the filter and the reference voltage buffer to avoid that the reference voltage buffer get an invalid reference voltage.
1. A reference voltage pre-processing circuit for a reference voltage buffer, comprising:
a first transistor, comprising a gate electrode configured to connect to a ground, a first electrode, and a second electrode;
a second transistor, comprising a gate electrode configured to connect to a voltage source, a first electrode connected to the second electrode of the first transistor, and a second electrode; and
an auxiliary voltage circuit, configured to interface the second transistor and the reference voltage buffer;
wherein the first transistor is a PMOS transistor, the second transistor is an NMOS transistor, one of the first electrode of the first transistor and the second electrode of the second transistor is configured to receive a first reference voltage and the other electrode is configured to provide a second reference voltage originating from the first reference voltage to the reference voltage buffer; and
wherein the auxiliary voltage circuit provides a third reference voltage to the reference voltage buffer if the second reference voltage is invalid and provides a fourth reference voltage to the reference voltage buffer if the second reference voltage is valid.
2. The reference voltage pre-processing circuit of claim 1 , wherein the first electrode of the first transistor is configured to receive the first reference voltage and the second electrode of the second transistor is configured to provide the second reference voltage to the reference voltage buffer.
3. The reference voltage pre-processing circuit of claim 2 , wherein the auxiliary voltage circuit comprises:
a third transistor, comprising a gate electrode connected to the second electrode of the second transistor, a first electrode configured to connect to the voltage source, and a second electrode connected to the gate electrode; and
a fourth transistor, comprising a gate electrode, a first electrode connected to the second electrode of the third transistor, and a second electrode connected to the gate electrode and the ground; and
wherein the third transistor is a PMOS transistor and the fourth transistor is a PMOS transistor.
4. The reference voltage pre-processing circuit of claim 3 , further comprising:
a capacitor, comprising a first electrode connected to the second electrode of the second transistor, and a second electrode configured to connect to the ground.
5. A reference voltage pre-processing method for a reference voltage buffer, comprising:
passing a first reference voltage to a second transistor via a first transistor;
providing a second reference voltage originating from the first reference voltage to the reference voltage buffer by the second transistor;
providing a third reference voltage to the reference voltage buffer by an auxiliary voltage circuit which interfaces the second transistor and the reference voltage buffer if the second reference voltage is invalid; and
providing a fourth reference voltage to the reference voltage buffer by the auxiliary voltage circuit if the second reference voltage is valid;
wherein one of the first transistor and the second transistor is a PMOS transistor and the other transistor is an NMOS transistor, the PMOS transistor comprises a gate electrode configured to connect to a ground, a first electrode, and a second electrode, and the NMOS transistor comprises a gate electrode configured to connect to a voltage source, a first electrode connected to the second electrode of the first transistor, and a second electrode; and
wherein one of the first electrode of the PMOS transistor and the second electrode of the NMOS transistor is configured to receive the first reference voltage and the other electrode is configured to provide the second reference voltage to the reference voltage buffer.
6. The reference voltage pre-processing method of claim 5 , wherein the first transistor is the PMOS transistor and the second transistor is the NMOS transistor, and wherein the first electrode of the PMOS transistor is configured to receive the first reference voltage and the second electrode of the NMOS transistor is configured to provide the second reference voltage to the reference voltage buffer.
7. The reference voltage pre-processing method of claim 6 , wherein the auxiliary voltage circuit comprises a third transistor and a fourth transistor, the third transistor is a PMOS transistor and comprises a gate electrode connected to the second electrode of the second transistor, a first electrode configured to connect to the voltage source, and a second electrode connected to the gate electrode, the fourth transistor is a PMOS transistor and comprises a gate electrode, a first electrode connected to the second electrode of the third transistor, and a second electrode connected to the gate electrode and the ground.
8. The reference voltage pre-processing method of claim 7 , further comprising:
stabilizing the third reference voltage or the fourth reference voltage by a capacitor which comprises a first electrode connected to the second electrode of the second transistor, and a second electrode configured to connect to the ground.