Phy control module for a multi-pair gigabit transceiver
View Patent ↗A method for controlling operation of a multi-pair gigabit transceiver. The multi-pair gigabit transceiver comprises a Physical Layer Control module (PHY Control), a Physical Coding Sublayer module (PCS) and a Digital Signal Processing module (DSP). The PHY Control receives user-defined inputs from the Serial Management module and status signals and diagnostics signals from the DSP and the PCS and generates control signals, responsive to the user-defined inputs, the status signals and diagnostics signals, to the DSP and the PCS.
1. A method for controlling operation of a multi-pair gigabit transceiver, the multi-pair gigabit transceiver comprising a Physical Layer control module (PHY control module), a Physical Coding Sublayer module (PCS module) and a digital signal processing module (DSP), the method comprising:
receiving at the PHY control module user-defined inputs from a serial management module and status signals from the DSP and the PCS module;
generating, at the PHY control module, control signals responsive to the user-defined inputs and the status signals; and
providing the control signals to the DSP and the PCS module.
2. The method of claim 1 wherein the multi-pair gigabit transceiver further comprises an auto-negotiation module, the method further comprising:
receiving at the PHY control module a link control signal from the auto-negotiation module to start operation of the PCS module and the DSP.
3. The method of claim 1 wherein the multi-pair gigabit transceiver further comprises a Gigabit Medium Independent Interface (GMII) module, the method further comprising:
receiving at the PHY control module a transmit enable signal from the GMII module to start transmission of data packets.
4. The method of claim 1 further comprising:
receiving a user-defined reset signal at the PHY control module; and
generating a control signal to reset the DSP and the PCS module.
5. The method of claim 1 wherein the control signals include a DSP/PCS reset signal to reset the DSP and the PCS module.
6. The method of claim 1 wherein the DSP comprises a set of echo cancellers and a set of near-end cross-talk (NEXT) cancellers, and wherein the control signals include echo and NEXT control signals to control convergence of the echo cancellers and NEXT cancellers, respectively.
7. The method of claim 1 wherein the DSP comprises a multi-dimensional decision feedback equalizer (DFE) and wherein the control signals include DFE control signals to control convergence of the multi-dimensional DFE.
8. The method of claim 1 wherein the DSP comprises a timing recovery (TR) module and wherein the control signals include TR control signals to control convergence of the timing recovery module.
9. A PHY control module for controlling operation of a multi-pair Ethernet transceiver, the multi-pair Ethernet transceiver comprising a Physical Coding Sublayer module (PCS module) and a Digital Signal Processing module (DSP), the PHY control module comprising:
a main state machine configured to receive user-defined inputs from a serial management module and status signals from the DSP and the PCS module, to generate control signals responsive to the user-defined input and the status signals, and to provide the control signals to the DSP and the PCS module.
10. The PHY control module of claim 9 wherein the multi-pair Ethernet transceiver further comprises an auto-negotiation module and wherein the main state machine receives a link control signal from the uto-negotiation module to start operation of the PCS module and the DSP.
11. The PHY control module of claim 9 wherein the multi-pair Ethernet transceiver further comprises a Gigabit Medium Independent Interface (GMII) module and wherein the main state machine receives a transmit enable signal from the GMII module to start transmission of data packets.
12. The PHY control module of claim 9 wherein the main state machine receives a user-defined reset signal and generates a control signal to reset the DSP and the PCS module.
13. The PHY control module of claim 9 wherein the control signals include a DSP/PCS reset signal to reset the DSP and the PCS module.
14. The PHY control module of claim 9 wherein the DSP comprises a set of echo cancellers and a set of near-end cross-talk (NEXT) cancellers, and wherein the control signals include echo and NEXT control signals to control convergence of the echo cancellers and NEXT cancellers, respectively.
15. The PHY control module of claim 9 wherein the DSP comprises a multi-dimensional decision feedback equalizer (DFE) and wherein the control signals include DFE control signals to control convergence of the multi-dimensional DFE.
16. The PHY control module of claim 9 wherein the DSP comprises a timing recovery (TR) module and wherein the control signals include TR control signals to control convergence of the timing recovery module.