Emulation system for evaluating digital data channel configurations
View Patent ↗Method and apparatus for evaluating different digital data channel configurations. A digital data channel stores input data to a recordable medium and retrieves readback data from the medium. The input data are arranged into an input sequence of symbols of selected symbol length, and the readback data are arranged into an output sequence of symbols of the selected symbol length. Comparing the output sequence to the input sequence allows identification of the number of erroneous symbols for the selected symbol length. Different input and output sequences are generated using different symbol lengths from the same input and output data. In this way, error rate performance can be predicted for different error correction code (ECC) and run length limited (RLL) encoding scheme combinations. The steps are carried out by an emulation system preferably comprising a field programmable gate array (FPGA) which inhibits and emulates selected portions of the digital data channel.
1. Method, comprising:
using a digital data channel to store input data to a data storage medium;
subsequently using the digital data channel to obtain output data from the medium;
after storing the input data in the using step, arranging to input data into a selected digital configuration from a plurality of different selectable digital configurations;
arranging the output data into the selected digital configuration; and
comparing the output data arranged in the selected digital configuration with the input data arranged in the selected digital configuration to determine an error rate performance.
2. The method of claim 1 wherein the comparing step is characterized by using a first error correction code (ECC) encoding methodology based on the selected digital configuration.
3. The method of claim 2 , wherein the comparing step is characterized by determining a number of errors in the output data in relation to a selected number of errors that can be detected by the first error correction code (ECC) encoding methodology.
4. The method of claim 1 , wherein the arranging the input and output data steps are characterized by sequences of multibit symbols each having a selected symbol length.
5. The method of claim 4 wherein the comparing step is characterized by predicting the error rate in relation to differences between the input sequence and the output sequence.
6. The method of claim 4 wherein the arranging the input and output data steps are characterized by sequences of multibit symbols each having a second selected symbol length.
7. The method of claim 6 wherein the comparing step is characterized by predicting error rate performance using a second error correction code (ECC) encoding methodology based on the second selected symbol length.
8. The method of claim 1 wherein the ranging the input and output data steps are characterized by performing run length limited (RLL) encoding upon the input data and inhibiting RLL decoding of the output data to reflect said RLL encoding.
9. The method of claim 1 , wherein the arranging the input and output data steps are characterized by arranging the data into a plurality of interleaves.
10. The method of claim 1 comprising concurrently inhibiting and emulating selected operation of the digital data channel.
11. The method of claim 1 wherein the comparing step is characterized by predicting the error rate in relation to only one selected digital configuration of the input and output data.
12. The method of claim 1 wherein the comparing step is characterized by predicting the error rate in relation to two or more selected digital configurations of the input and output data.